Chapter 7 Memory Hierarchy

11998 Morgan Kaufmann Publishers

Chapter 7Memory Hierarchy

Outline

Technology Trends

Processor Memory Latency Gap

Time of a full cache miss in instructions executed• 1st Alpha: 340 ns/5.0 ns = 68 clks x 2 (136 instr.)• 2nd Alpha: 266 ns/3.3 ns = 80 clks x 4 (320 instr.)• 3rd Alpha: 180 ns/1.7 ns =108 clks x 6 (648 instr.)

Solution: Memory Hierarchy

Speed: Fastest Slowest Size: Smallest Biggest Cost: Highest Lowest

Memory Hierarchy: Principle

Why Hierarchy Works?

How Does It Work?

Speed (ns): 1’s 10’s 100’s 10,000,000’s 10,000,000,000’s (10’s ms) (10’s sec)Size(bytes): 100’s K’s M’s G’s T’s

How Is the Hierarchy Managed?

Memory Hierarchy Technology

Memory Hierarchy: Terminology

4 Questions for Hierarchy Design

Memory System Design

Summary of Memory Hierarchy

Outline

Basics of Cache

Hits and Misses

Avoid Waiting for Memoryin Write Through

Exploiting Spatial Locality

Block Size Tradeoff

Block Size

Memory Design to Support Cache

Interleaving for Bandwidth

Cache Performance

Improving Cache Performance

Reduce Miss Ratio with Associativity

Set-Associative Cache

Possible Associativity Structures

Block Placement

Data Placement Policy

Cache Block Replacement

Comparing the Structures

A 4-Way Set-Associative Cache

Reduce Miss Penalty with Multilevel Caches

Sources of Cache Misses

Cache Design Space

Cache Summary

Outline

Virtual Memory

Why Virtual Memory?

Basic Issues in Virtual Memory

Paging

Key Decisions in Paging

Choosing the Page Size

Page Tables

Page Fault: What Happens When You Miss?

Handling Page Faults

Page Replacement: 1-bit LRU

Architecture part: support dirty and used bits in the page table (how?)=> may need to update PTE on any instruction fetch, load, store

Impact of Paging (I)

Hashing: Inverted Page Tables

Two-level Page Tables

Impact of Paging (II)

Making Address Translation Practical

Translation Lookaside Buffer

TLB of MIPS R2000

TLB in Pipeline

Processing inTLB+Cache

Possible Combinations of Events

Virtual Address and Cache

Virtually Addressed Cache

An Alternative: Overlapped TLB andCache Access

IF cache hit AND (cache tag = PA) then deliver data to CPUELSE IF [cache miss OR (cache tag = PA)] and TLB hit THENaccess memory with the PA from the TLB ELSE do standard VA translation

Problem with Overlapped Access

Protection with Virtual Memory

A Common Framework for MemoryHierarchies

Modern Systems

Challenge in Memory Hierarchy

Summary

Summary (cont.)

Chapter 7 Memory Hierarchy

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