CE1110: Digital Logic Design

Sequential Circuits

• Design a FSM that detects 3 or more consecutive ones from a serial input x.

Design Example

X Y3 ones detector

Steps:1. Understand the statement of the Specification 2. Obtain a state diagram of the FSM from the specification3. Perform state assignment4. Determine the number of flip flop (to repre-

sent 4 states => 2 flip flops)5. Choose type of flip-flop if not given (for example we will choose D-FF)

1. Derive state diagram

S000

S101

1/0

0/0

• We will begin with assumption that no input entered to system, we will give this state name S0

• Our system will stop at S0 if the input to the system is always ‘0’• If the system has ‘1’ input a new states created which represent the state that

you have only 1 we will call it S1

Input/Output

• If the system was in state S1 and a ‘0’ entered the system, it must be returned to S0 as we are searching for 3 consecutive ones.

• Else if another ‘1’ entered the system it will go to new state that represent existing of two ones consecutive we will call it S2.

• If the system was in state S2 and ‘0’ entered the system it will return to S0.• Else if ‘1’ entered to the system it will move to a new state that represent the existing of

three consecutive ones S3 and the output would be equal to y=‘1’. • If the system has more ones as an input it will continue at S3 and output y=‘1’• Finally, if we have input X=‘0’ to the system, it will goes to the starting state S0

0/0

S000

S101

S210

0/0

1/01/0

1/1S311

0/00/0

1/1

Present State

Input Next State

Out FF Inputs

A B X A B y DA DB

0 0 0 0 0 0 0 0

0 0 1 0 1 0 0 1

0 1 0 0 0 0 0 0

0 1 1 1 0 0 1 0

1 0 0 0 0 0 0 0

1 0 1 1 1 1 1 1

1 1 0 0 0 0 0 0

1 1 1 1 1 1 1 1

2. Construct the state table

Q(t) Q(t+1) D

0 0 0

0 1 1

1 0 0

1 1 1

D–FF Excitation Table

3. Drive simplified State Equations

Note: Output here depends on the present state (A(t)) and input (x)

4: Implement the FSM

Sequential Circuit Analysis (cont.)– Generate State Diagram

• Circles (nodes) represent current or present state values

• Lines (arcs) represent how state and output values change

– Given the current state and current inputs, the next state and output values are indicated by the associated arc

• State diagram can have different forms depending on the type of sequential circuit output.

PresentStateValue

NextStateValue

Inputs/outputs

27

Example

• Analyze the following sequential circuit

• How to analyze any sequential circuit

• You need to know :– State equation – State diagram– State table

1- Determine State equation

• From the circuit get the logic equations of the input of flip-flops A(t+1) & B(t+1) and output y(t)

• FF input equationsA(t+1) = A(t)X(t)+B(t)X(t)B(t+1) = A’(t)X(t)

• Output equationY(t) = X’(t)(B(t)+A(t))

A(t+1)

B(t+1) (t)

(t)

(t)

2-Create State table• From logic equation & characteristics table of flip-flop create State table

• FF input equations

A(t+1) = AX+BX

B(t+1) = A’X• Output equation

Y = X’(B+A)

• D flip-flop characteristic table

3-Construct the state diagram

00 10

01 11

0/0

Input/Output

1/0 0/1

1/0

0/11/0

0/11/0

Registers• There are also another applications for Flip-flops

like Registers– “Register” is a small amount of storage available on the

CPU whose contents can be accessed more quickly than storage available elsewhere. Typically, this specialized storage is not considered part of the normal memory range for the machine.

– Registers are normally measured by the number of bits they can hold (ex. 8-bits or 32-bits register)

– They have been implemented using individual flip-flops

• What’s the main structure of the register from inside? And what’s the types of registers?

RegistersAn n-bit register consists of a group n flip -flops capable

of storing n bits of binary info.All Flip-flops are connected to one clock source Each flip-flop can store one bit of Info.Clear signal during normal operation is set to highThe clear input is useful for clearing all the content of the

register to all 0’sProblem: Typically don’t want to load every clock

Solution: use a external signal to control the opera-tion of the load

Registers with Parallel Load 1

1

0

0

0

1

Shift Registers A register capable of shifting its binary information in one or both direction

is called a shift register A chain of flip-flops in cascade

010

SI

CLK

Qa

Qb

etc

0

Qa Qb Qc

Universal Shift Registers

S1 S2 Action

0 0 No Change

0 1 Shift Right

1 0 Shift Left

1 1 Parallel Load

No Change Shift Right Shift Left Parallel Load Need a Clear and Clock