Post on 26-May-2020
Young Won Lim5/24/16
Cache Memory
Young Won Lim5/24/16
Copyright (c) 2010-2016 Young W. Lim.
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Memory 3 Young Won Lim5/24/16
Address is used as an index to a data array
Memory Unit2k words
n-bit per word
Input n-bit Data
Output n-bit Data
0000000100100011010001010110011110001001101010111100110111101111
k-bit Address n-bit data
24 words
k-bit Address
Read
Write
index
Memory 4 Young Won Lim5/24/16
MM Address Decoder
k-bit Address
n-bit data
en.wikipedia.org
AddressDecoder
Memory 5 Young Won Lim5/24/16
Cache : Storing a partial copy of MM
0000000100100011010001010110011110001001101010111100110111101111
(MM Address, Data) pair
dataMM Address
010001011000100110101011
Cache Memory
Main Memory
Memory 6 Young Won Lim5/24/16
Cache Memory : two components
Cache Memory
Tag Cache Directory
DataMM Address
Data
Cache Array
Memory 7 Young Won Lim5/24/16
Accessing Cache Memory : Address Matching
CacheMemory
Tag MemoryCache Directory
DataMM Address
DataCache Array
Address
Match
Hit
from CPU
to / from CPU
Cache Memory 8 Young Won Lim5/24/16
CAM (Content Addressable Memory) Interface
DIN[M:0]WR_ADDR[logN:0]DATA_MASK[M:0]CMP_DIN[M:0]CMP_DATA_MASK[M:0]
CLKENWE
MATCH_ADDR[J:0]MULTIPLE_MATCH
SINGLE_MATCH
BUSYREAD_WARNING
xapp1151_Param_CAM.pdf
Xilinx CAM
Cache Memory 9 Young Won Lim5/24/16
CAM Read Operation – Search a key
DIN[M:0]
CLKENWE
MATCH_ADDR[J:0]MULTIPLE_MATCH
SINGLE_MATCH
xapp1151_Param_CAM.pdf
CAM Address
0
Search Data
CA
M A
ddre
ss
Search DataSearch Data
match?
0
Cache Memory 10 Young Won Lim5/24/16
Write Operation
DIN[M:0]WR_ADDR[logN:0]
CLKENWE
xapp1151_Param_CAM.pdf
CAM AddressWrite Data
CA
M A
ddre
ss
Search Data
write
10
Cache Memory 11 Young Won Lim5/24/16
Simultaneous Read / Write
DIN[M:0]WR_ADDR[logN:0]DATA_MASK[M:0]CMP_DIN[M:0]CMP_DATA_MASK[M:0]
CLKENWE
BUSYREAD_WARNING
xapp1151_Param_CAM.pdf
1
EN=1 simultaneous write/read
Simultaneous Read/Write Simultaneous write and search operationsWith an output to warn the user of possible collisionRead warning flag:
The data applied to the CAM for a readMatches the data that is currently being written into the CAMBy unfinished write operation
Search Data
Write DataCAM Address
MATCH_ADDR[J:0]MULTIPLE_MATCH
SINGLE_MATCH
CAM Address
Cache Memory 12 Young Won Lim5/24/16
Ternary Mode
DIN[M:0]WR_ADDR[logN:0]DATA_MASK[M:0]CMP_DIN[M:0]CMP_DATA_MASK[M:0]
CLKENWE
MATCH_ADDR[J:0]MULTIPLE_MATCH
SINGLE_MATCH
BUSYREAD_WARNING
xapp1151_Param_CAM.pdf
1
Cache Address
EN=1 simultaneous write/read
DIN[M:0] Data in Bus The data to be written into The data read from the CAM
Simultaneous read/write modeCMP_DIN for the read operation
Standard Ternary modeDIN DATA_MASK0 0 01 0 10 1 X1 1 X
CMP_DIN[M:0] Compare Data In BusSimultaneous read/write
The data read from the CAMTernary mode
One of the two input busesTo determine the bit value During read operation
Cache Memory 13 Young Won Lim5/24/16
SRAM Cell
CMOS VLSI Design 4th ed, Weste
bit bit_b
word
Cache Memory 14
R
Sinput
select
output
Read / Write
Read / Write = 1→ READ op
Read / Write = 0→ WRITE op
BC
select
Read / Write
input output
SRAM Bit Cell RTL Model
Q
en.wikipedia.org
Cache Memory 15
R
Sinput
select
output
Read / Write = 1→ READ op
SRAM Bit Cell Read & Write Operations
Q
R
SInput x
select
output
Read / Write = 0→ WRITE op
Q0
0
0
x
xb
1
10
S=1
R=0
SET
S=0
R=1
RESET
S=0
R=0
HOLD Q=old Q
Q=old Q
Q=1
Q=0
Q=0
Q=1
Input x=1
Input x=0
en.wikipedia.org
Cache Memory 16 Young Won Lim5/24/16
10T CAM Cell
bit bit_b
match
word
CMOS VLSI Design 4th ed, Weste
Cache Memory 17
BC
select
Read / Write
input output
SRAM Bit Cell RTL Model
match
Cache Memory 18
R
Sinput
select
Read / Write
Read / Write = 1→ READ op
Read / Write = 0→ WRITE op
BC'
select
read / write
input
CAM Bit Cell RTL Model
Q
match
match
Cache Memory 19
CAM Bit Cell RTL Model – Read / Write Operations
R
Sinput
select
Q
R
Sinput
select
Q
S=1
R=0
SET
S=0
R=1
RESET
S=0
R=0
HOLD Q=old Q
Q=old Q
Q=1
Q=0
Q=0
Q=1
Input x=1
Input x=0
Read / Write = 1→ READ op
Read / Write = 0→ WRITE op
match_out
0
0
0 1
x
xb
0
match_out
0
Cache Memory 20
BC
select
Read / Write
input output
2x2 CAM Bit Cell RTL Model
match
BC
select
Read / Write
Ain1
output
match
BC
select
Read / Write
input output
match
BC
select
Read / Write
input output
match
select
select
r/w
Ain0
CAM Address
Cache Memory 21
Diagram for a Cache Memory with 2 lines
4-bit word
D3 D2 D1 D0
O3 O2 O1 O0R/W
BCBC
BCBC
BCBC
BCBC
BCBC
BCBC
BCBC
BCBC
BC
select
Read / Write
input output
match
BC
select
Read / Write
output
match
BC
select
Read / Write
input output
match
BC
select
Read / Write
input output
match
select
select
r/w
A1 A0
000801
10AB11
dataMM Address
0801AB11
Cache Memory
Main Memory
Cache Memory 22 Young Won Lim5/24/16
Cache Organization
8 sets 1-way 1 line / set
4 sets 2-way 2 lines / set
2 sets 4-way 4 lines / set
1 set 8-way 8 lines / set
Cache Memory 23 Young Won Lim5/24/16
Direct Mapping
8 sets 1-way 1 line / set
CacheMemory
MainMemory
Cache Memory 24 Young Won Lim5/24/16
2-Way Set Associative Mapping
4 sets 2-way 2 lines / set
CacheMemory
MainMemory
Cache Memory 25 Young Won Lim5/24/16
4-way Set Associative Mapping
2 sets 4-way 4 line / set
CacheMemory
MainMemory
Cache Memory 26 Young Won Lim5/24/16
Fully Associative Mapping
1 sets 8-way 8 line / set
CacheMemory
MainMemory
Cache Memory 27 Young Won Lim5/24/16
Tag Field
8 sets 1-way 1 line / set
4 sets 2-way 2 lines / set
2 sets 4-way 4 lines / set
1 set 8-way 8 lines / set
tag set block
Cache Memory 28 Young Won Lim5/24/16
Cache Mapping Method (set-view)
8 sets 1-way 1 line / set
4 sets 2-way 2 lines / set
2 sets 4-way 4 lines / set
1 set 8-way 8 lines / set
Cache Memory 29 Young Won Lim5/24/16
Cache Mapping Method (set-view)
8 sets 1-way 1 line / set
4 sets 2-way 2 lines / set
2 sets 4-way 4 lines / set
1 set 8-way 8 lines / set
Cache Memory 30 Young Won Lim5/24/16
Cache Mapping Method (way-view)
8 sets 1-way 1 line / set
4 sets 2-way 2 lines / set
2 sets 4-way 4 lines / set
1 set 8-way 8 lines / set
Cache Memory 31 Young Won Lim5/24/16
CAM (Content Addressable Memory)
Cache Memory 32 Young Won Lim5/24/16
CAM (Content Addressable Memory)
Cache Memory 33 Young Won Lim5/24/16
CAM (Content Addressable Memory)
Cache Memory 34 Young Won Lim5/24/16
CAM (Content Addressable Memory)
Cache Memory 35
BC
select
Read / Write
input output
SRAM Bit Cell RTL Model
match_out
match_in
out
Cache Memory 36
R
Sinput
select
output
Read / Write
Read / Write = 1→ READ op
Read / Write = 0→ WRITE op
BC'
select
read / write
input output
CAM Bit Cell RTL Model
Q
match_out
match_out
match_in
match_in
Cache Memory 37
CAM Bit Cell RTL Model – Read / Write Operations
R
Sinput
select
output
Q
R
Sinput
select
output
Q
S=1
R=0
SET
S=0
R=1
RESET
S=0
R=0
HOLD Q=old Q
Q=old Q
Q=1
Q=0
Q=0
Q=1
Input x=1
Input x=0
Read / Write = 1→ READ op
Read / Write = 0→ WRITE op
match_out
0
0
0 1
x
xb
0
0
match_out
0
match_in match_in
Cache Memory 38
BC
select
Read / Write
input output
2x2 CAM Bit Cell RTL Model
match_out
match_inout
BC
select
Read / Write
Ain1
output
match_out
match_inout
BC
select
Read / Write
input output
match_out
match_inout
BC
select
Read / Write
input output
match_out
match_inout
select
select
r/w
Ain0
Aout1 Aout0
Young Won Lim5/24/16
References
[1] http://en.wikipedia.org/[2] https://en.wikiversity.org/wiki/The_necessities_in_SOC_Design[3] https://en.wikiversity.org/wiki/The_necessities_in_Digital_Design[4] https://en.wikiversity.org/wiki/The_necessities_in_Computer_Design[5] https://en.wikiversity.org/wiki/The_necessities_in_Computer_Architecture[6] https://en.wikiversity.org/wiki/The_necessities_in_Computer_Organization[7] https://en.wikiversity.org/wiki/Understanding_Embedded_Software[8] Digital Systems, Hill, Peterson, 1987