Axel Jantsch1

NOCARCNetwork on Chip Architecture

KTH, VTT

Nokia, Ericsson, Spirea

TEKES, Vinnova

Axel Jantsch 2 20th Sept. 2002

Outline NoC Architecture overview Activities Switch Design

Buffer-lessHot-potato routingStress sensitive routing

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NoC Architecture Overview

Switch

Resource

•Message passing communication infrastructure

•Physical-Architectural Level design integration

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Resource-Network Interface

Resource

RNI

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Concept of Region

Resources larger than a slot

FPGA

Memory

Parallel processor

Wrapper will make the region transparent to outside traffic

Communication within a region could happen differently than rest of the network

Wrapper

Axel Jantsch 6 20th Sept. 2002

Quick Summary of Activities NoC Architecture Implementation

Physical feasibility study Buffer Less Switch Design

NoC Evaluation Ns-2 based NoC Simulator Dedicated simulator for NoC

Nostrum protocol stack 5-layered protocol stack

Two Phase Design Methodology Special Purpose NoC Region NoC Specific Fault Model and Error Protection NoC Specific Quasi-synchronous Clocking

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Buffer Less Switch

Switch

Packet

Packet

Packet

PacketPacket

Packet

Packet

Packet

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• Load information sent between switches, stress value1. no Stress value

2. with Stress value

3. averaged Stress value (four cycles)

• Better routing decisions for intermediate load

• Larger design

Load distribution using Stress values

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Final implementation

Axel Jantsch 10 20th Sept. 2002

Results of synthesis

constraint total combined logic critical path gate depth

optimised for area 13 964 79

optimised for speed 21 029 48

(using Synopsys)

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Maximum probability for various mesh sizes

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Network delay

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Number of packets in centre FIFO

p=0.47 p=0.48 p=0.49 p=0.50

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Average load in FIFOs with no Stress value

max=3.2

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Average load in FIFOs using Stress value

max=0.9

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Average load in FIFOs using averaged Stress value

max=0.15

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Comparing results

2115.0

2.3 times longer waiting time

max=3.2 max=0.9 max=0.15

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Conclusion

A buffer-less switch is feasible Very low cost and high performance Stress values is a simple control mechanism It increases maximum load by 20% It decreases the maximum latency by factor of 20