Antifuse Macro Library Guide

for Software v8.1

Table of Contents

2 Antifuse Macro Library Guide for Software v8.1

Part Number: 5029009-22

Release: December 2007

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Table of Contents

Introduction

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7How to Use this Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Advanced Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8HDL Instantiation of Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Migration Between Families . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

List of Combinational Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9List of Sequential Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13List of CC Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15List of RAM Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17List of Input/Output Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Alphabetical List of Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Combinational/Sequential Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Combinational, AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29Combinational, AND-OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37Combinational, AND-OR-INVERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53Combinational, AND-OR-INVERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57Combinational, AND-XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58Combinational, AND-XOR-INVERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58Combinational, 3-Input Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68Combinational, Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70Carry Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87Sequential, D-Type Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89Sequential D-Type Flip-Flop with Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95Sequential, D-Type Flip-Flop with Multiplexed Data . . . . . . . . . . . . . . . . . . . . . . . .107Sequential, D-Type Flip-Flop with Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122Sequential, D-Type Flip-Flop with Preset and Clea r . . . . . . . . . . . . . . . . . . . . . . . .130Sequential, Data Latc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131Sequential, Data Latch with Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136Sequential, Data Latch with Enable and Clear . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139

Antifuse Macro Library Guide for Software v8.1 3

Table of Contents

Sequential, Data Latch with Enable and Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142Data Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .144Data Latch with Multiplexed Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147Sequential, Data Latch with Preset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153Sequential, JK Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155Combinational, Wide Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156Combinational, Clock Net Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160Combinational, Half Adder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163Combinational, Inverters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .165JK Flip-Flop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168Combinational, AND-OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172Combinational, AND-OR-INVERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177Combinational, Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178Combinational, NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .181Combinational, NOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .189Combinational, OR-AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .196Combinational, OR-AND-INVERT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202Combinational, OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207Combinational, XOR-AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217Combinational, XNOR-AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218Combinational, XNOR-NAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .219Combinational, XNOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .220Combinational, XOR-OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221Combinational, XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222Combinational, Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225

CC-Module Flip Flops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

Memory Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

RAM Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .240FIFO Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

I/O Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Input/Output, General Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256ACT 2/XL/DX/MX I/O Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264ACT 3 I/O Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .271Axcelerator Input IO Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289Bi-Directional IO Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290Clock Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293HClock Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294Output Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295Tri-State Buffer Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296Differential IO Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298

Table of Contents

DDR Macro . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300

Carry Chain Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301

Carry Chain Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302

PLL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313

PLL Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314

IntroductionThis guide includes macros for all Actel antifuse devices. For Flash devices, see the Flash Macro Library

Guide.

Definitions

MacrosThe Macro library consists of logic elements constructed of one or more ACT family modules. Modules may be of type sequential or combinatorial. The relative placement of two module-macros is predefined. The timing characteristics are a function of the fanout on the output of the macro.

SmartGen CoresSmartGen cores are described in Actel’s publication SmartGen Cores Reference Guide.

How to Use this Guide

Family Inclusion IndicatorIn the titlebar of each macro is a list indicating whether the cell is a member of the ACT 1, ACT 2, 3200DX, ACT 3, MX, SX, SX-A, eX, or Axcelerator library.

Guidelines1. All input pin loading is assumed to be a single load except macros that are built using two combinational modules or one sequential and one combinatorial module. These macros are assumed to have a load of two on some of their input pins.

2. All macros have output pin loading of zero except for the sequential macros that are built using two combinational modules only. These macros have an output pin loading of one.

3. All macros have logic levels equal to one except cells with pin delays of two. A “2” is added to the corresponding symbol in the macro section of this manual.

Truth Table NomenclatureTruth tables are arranged with Inputs before Outputs. The following symbol definitions apply.

↑ denotes rising edge clock

↓ denotes falling edge clock

X in an input column denotes a ‘don't care’ or logic simulation state ‘un-

known’

!Q denotes Q not

Pin Delay AnnotationTwo-module combinatorial macros contain extra delay on some or all of the pins. If a macro symbol in this guide displays a “2” on a pin, then two levels of logic delay exist on the input to output path.

Note: Many two-level logic functions in one family are implemented in a single module in another family, hence the “2” may apply to specific families only.

Restrictions

Special I/OsSome I/O pins are able to connect to global control signals such as clock or clear. These I/O pins may be used as “normal” data input/output buffers or they may be used as “special” pins. The following constraints apply to I/O pins used as “special” pins.

All ACT 2, 3200DX, ACT 3, MX, SX, SX-A, and eX register cells may be clocked by either of the two global clock networks by connecting their CLK input to the output of a CLKBUF, CLKBIBUF, or CLKINT macro.

All ACT 2, 3200DX, ACT 3, MX, SX, SX-A, and eX register cells may be globally preset, reset or enabled by connecting the PRE, CLR, or E input to the output of a CLKBUF, CLKBIBUF, CLKINT macro.

All ACT 2, 3200DX, ACT 3, MX, SX, SX-A and eX I/O three-state buffers may be globally enabled by connecting their E input to the output of a CLKBUF, CLKBIBUF, OR CLKINT macro.

All ACT 3, SX, SX-A and eX register cells composed of sequential modules may be clocked by high speed clock buffer network by connecting their CLK input to the output of a HCLKBUF macro.

ACT 3 registered I/O macros may only be clocked by the IOCLKBUF macro.

ACT 3 registered I/O macros may only be asynchronously set or preset by the IOPCL macro.

Introduction

Advanced Application NotesFor Advanced Application notes, please go to the Actel website at http://www.actel.com.

HDL Instantiation of MacrosRefer to the HDL Coding Style Guide for information on instantiating macros.

Migration Between FamiliesActel provides the capability of migrating a netlist created for one family to another family in some cases. Macros listed in this manual as being available in the old family will not be shown as available in the new family when the new macro is inefficient or when the function can be better implemented with different macros, however, the macro may be available in the

new family. Such macros are not recommended for new designs.

In all cases, if an HDL description is available, it is best to resynthesize, targeting the new family.

If an HDL description is not available, it is still generally best to do gate level retargeting to the new family.

If neither of the above is done, a netlist created for one family may be used in another family as follows: No special procedures are needed to use the netlist in Designer, but a migration library must be enabled in CAE environments as explained in individual CAE Interface Guides.

* Except registered I/O, IOCLK, and IOPCL

** Except QCLK and RAM

Target Family

Original Family ACT 1/MXACT 2/

3200DX/MXACT 3 SX SX-A eX

ACT 1 or MX X YES YES NO NO NO

ACT 2, 1200XL, 3200DX, MX

NO X YES** YES** YES** YES**

ACT 3 NO NO X YES* YES* YES*

SX NO NO NO X YES YES

SX-A NO NO NO YES** X YES

eX NO NO NO YES YES X

List of Combinational Macros

AND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 29AND2A . . . . . . . . . . . . . . . . . . . . . . . . . . 29AND2B . . . . . . . . . . . . . . . . . . . . . . . . . . 30AND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 30AND3A . . . . . . . . . . . . . . . . . . . . . . . . . . 31AND3B . . . . . . . . . . . . . . . . . . . . . . . . . . 31AND3C . . . . . . . . . . . . . . . . . . . . . . . . . . 32AND4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 32AND4A . . . . . . . . . . . . . . . . . . . . . . . . . . 33AND4B . . . . . . . . . . . . . . . . . . . . . . . . . . 33AND4C . . . . . . . . . . . . . . . . . . . . . . . . . . 34AND4D . . . . . . . . . . . . . . . . . . . . . . . . . . 34AND5A . . . . . . . . . . . . . . . . . . . . . . . . . . 35AND5B . . . . . . . . . . . . . . . . . . . . . . . . . . 35AND5C . . . . . . . . . . . . . . . . . . . . . . . . . . 36A01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36AO10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37AO11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37AO12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38AO13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38AO14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39AO15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39AO16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40AO17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40AO18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41AO1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 41AO1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 42AO1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 42AO1D . . . . . . . . . . . . . . . . . . . . . . . . . . . 43AO1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43AO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44AO2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 44AO2B . . . . . . . . . . . . . . . . . . . . . . . . . . . 45AO2C . . . . . . . . . . . . . . . . . . . . . . . . . . . 45AO2D . . . . . . . . . . . . . . . . . . . . . . . . . . . 46AO2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46AO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47AO3A . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

AO3B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48AO3C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48AO4A . . . . . . . . . . . . . . . . . . . . . . . . . . . 49AO5A . . . . . . . . . . . . . . . . . . . . . . . . . . . 49AO6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50AO6A . . . . . . . . . . . . . . . . . . . . . . . . . . . 50AO7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51AO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51AO9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52AOI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52AOI1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 53AOI1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 53AOI1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 54AOI1D . . . . . . . . . . . . . . . . . . . . . . . . . . . 54AOI2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 55AOI2B . . . . . . . . . . . . . . . . . . . . . . . . . . . 55AOI3A . . . . . . . . . . . . . . . . . . . . . . . . . . . 56AOI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56AOI4A . . . . . . . . . . . . . . . . . . . . . . . . . . . 57AOI5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57AX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58AX1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58AX1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59AX1C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59AX1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60AX1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60AXO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61AXO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61AXO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62AXO5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62AXO6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63AXO7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63AXOI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 64AXOI2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 64AXOI3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 65AXOI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 65AXOI5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 66AXOI7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

BUFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67BUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67BUFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68CLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . 68HCLKINT . . . . . . . . . . . . . . . . . . . . . . . . . 69CLKINTI . . . . . . . . . . . . . . . . . . . . . . . . . . 69CM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70CM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71CM8A . . . . . . . . . . . . . . . . . . . . . . . . . . . 72CM8F . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73CM8INV . . . . . . . . . . . . . . . . . . . . . . . . . 74CMA9 . . . . . . . . . . . . . . . . . . . . . . . . . . . 74CMAF . . . . . . . . . . . . . . . . . . . . . . . . . . . 75CMB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 75CMB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 76CMBB . . . . . . . . . . . . . . . . . . . . . . . . . . . 76CMBF . . . . . . . . . . . . . . . . . . . . . . . . . . . 77CMEA . . . . . . . . . . . . . . . . . . . . . . . . . . . 77CMEB . . . . . . . . . . . . . . . . . . . . . . . . . . . 78CMEE . . . . . . . . . . . . . . . . . . . . . . . . . . . 78CMEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79CMF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79CMF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80CMF3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80CMF4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81CMF5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81CMF6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82CMF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82CMF8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83CMF9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83CMFA . . . . . . . . . . . . . . . . . . . . . . . . . . . 84CMFB . . . . . . . . . . . . . . . . . . . . . . . . . . . 84CMFC . . . . . . . . . . . . . . . . . . . . . . . . . . . 85CMFD . . . . . . . . . . . . . . . . . . . . . . . . . . . 85CMFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86CS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86CS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87CY2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87CY2B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89DLEB . . . . . . . . . . . . . . . . . . . . . . . . . . . 144DLEC . . . . . . . . . . . . . . . . . . . . . . . . . . . 144DLM . . . . . . . . . . . . . . . . . . . . . . . . . . . 145DLM2 . . . . . . . . . . . . . . . . . . . . . . . . . . 145

DLM2A . . . . . . . . . . . . . . . . . . . . . . . . . 147DLM2B . . . . . . . . . . . . . . . . . . . . . . . . . 147DLM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 148DLM3A . . . . . . . . . . . . . . . . . . . . . . . . . 148DLM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149DLM4A . . . . . . . . . . . . . . . . . . . . . . . . . 149DLM8A . . . . . . . . . . . . . . . . . . . . . . . . . 150DLM8B . . . . . . . . . . . . . . . . . . . . . . . . . 151DLMA . . . . . . . . . . . . . . . . . . . . . . . . . . 152DLME1A . . . . . . . . . . . . . . . . . . . . . . . . 152DLP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 153DLP1A . . . . . . . . . . . . . . . . . . . . . . . . . . 153DLP1B . . . . . . . . . . . . . . . . . . . . . . . . . . 154DLP1C . . . . . . . . . . . . . . . . . . . . . . . . . . 154DLP1D . . . . . . . . . . . . . . . . . . . . . . . . . . 155DLP1E . . . . . . . . . . . . . . . . . . . . . . . . . . 155DXAND7 . . . . . . . . . . . . . . . . . . . . . . . . 156DXAX7 . . . . . . . . . . . . . . . . . . . . . . . . . 157DXNAND7 . . . . . . . . . . . . . . . . . . . . . . . 157FA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158FA1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 158FA1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 159FA2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 159GAND2 . . . . . . . . . . . . . . . . . . . . . . . . . 160GMX4 . . . . . . . . . . . . . . . . . . . . . . . . . . 160GNAND2 . . . . . . . . . . . . . . . . . . . . . . . . 161GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161GNOR2 . . . . . . . . . . . . . . . . . . . . . . . . . 162GOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 162GXOR2 . . . . . . . . . . . . . . . . . . . . . . . . . 163HA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163HA1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 164HA1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 164HA1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 165INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . 166INVA . . . . . . . . . . . . . . . . . . . . . . . . . . . 166JKF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167JKF1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 168JKF2A . . . . . . . . . . . . . . . . . . . . . . . . . . 168JKF2B . . . . . . . . . . . . . . . . . . . . . . . . . . . 169JKF2C . . . . . . . . . . . . . . . . . . . . . . . . . . . 169JKF2D . . . . . . . . . . . . . . . . . . . . . . . . . . 170

JKF3A . . . . . . . . . . . . . . . . . . . . . . . . . . 170JKF3B . . . . . . . . . . . . . . . . . . . . . . . . . . 171JKF3C . . . . . . . . . . . . . . . . . . . . . . . . . . 171JKF3D . . . . . . . . . . . . . . . . . . . . . . . . . . 172JKF4B . . . . . . . . . . . . . . . . . . . . . . . . . . 173JKFPC . . . . . . . . . . . . . . . . . . . . . . . . . . 173MAJ3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 174MAJ3X . . . . . . . . . . . . . . . . . . . . . . . . . 174MAJ3XI . . . . . . . . . . . . . . . . . . . . . . . . . 175MIN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 175MIN3X . . . . . . . . . . . . . . . . . . . . . . . . . . 176MIN3XI . . . . . . . . . . . . . . . . . . . . . . . . . 177MX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 178MX2A . . . . . . . . . . . . . . . . . . . . . . . . . . 178MX2B . . . . . . . . . . . . . . . . . . . . . . . . . . 179MX2C . . . . . . . . . . . . . . . . . . . . . . . . . . 179MX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 180MXC1 . . . . . . . . . . . . . . . . . . . . . . . . . . 180MXT . . . . . . . . . . . . . . . . . . . . . . . . . . . 181NAND2 . . . . . . . . . . . . . . . . . . . . . . . . . 181NAND2A . . . . . . . . . . . . . . . . . . . . . . . . 182NAND2B . . . . . . . . . . . . . . . . . . . . . . . . 182NAND3 . . . . . . . . . . . . . . . . . . . . . . . . . 183NAND3A . . . . . . . . . . . . . . . . . . . . . . . . 183NAND3B . . . . . . . . . . . . . . . . . . . . . . . . 184NAND3C . . . . . . . . . . . . . . . . . . . . . . . . 184NAND4 . . . . . . . . . . . . . . . . . . . . . . . . . 185NAND4A . . . . . . . . . . . . . . . . . . . . . . . . 185NAND4B . . . . . . . . . . . . . . . . . . . . . . . . 186NAND4C . . . . . . . . . . . . . . . . . . . . . . . . 186NAND4D . . . . . . . . . . . . . . . . . . . . . . . . 187NAND5B . . . . . . . . . . . . . . . . . . . . . . . . 187NAND5C . . . . . . . . . . . . . . . . . . . . . . . . 188NAND5D . . . . . . . . . . . . . . . . . . . . . . . . 188NOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 189NOR2A . . . . . . . . . . . . . . . . . . . . . . . . . 189NOR2B . . . . . . . . . . . . . . . . . . . . . . . . . 190NOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . 191NOR3A . . . . . . . . . . . . . . . . . . . . . . . . . 191NOR3B . . . . . . . . . . . . . . . . . . . . . . . . . 192NOR3C . . . . . . . . . . . . . . . . . . . . . . . . . 192NOR4 . . . . . . . . . . . . . . . . . . . . . . . . . . 193NOR4A . . . . . . . . . . . . . . . . . . . . . . . . . 193

NOR4B . . . . . . . . . . . . . . . . . . . . . . . . . . 194NOR4C . . . . . . . . . . . . . . . . . . . . . . . . . . 194NOR4D . . . . . . . . . . . . . . . . . . . . . . . . . 195NOR5B . . . . . . . . . . . . . . . . . . . . . . . . . . 195NOR5C . . . . . . . . . . . . . . . . . . . . . . . . . . 196NOR5D . . . . . . . . . . . . . . . . . . . . . . . . . 196OA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197OA1A . . . . . . . . . . . . . . . . . . . . . . . . . . 198OA1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 198OA1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 199OA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199OA2A . . . . . . . . . . . . . . . . . . . . . . . . . . 200OA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200OA3A . . . . . . . . . . . . . . . . . . . . . . . . . . 201OA3B . . . . . . . . . . . . . . . . . . . . . . . . . . . 201OA4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202OA4A . . . . . . . . . . . . . . . . . . . . . . . . . . 202OA5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203OAI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 203OAI2A . . . . . . . . . . . . . . . . . . . . . . . . . . 204OAI3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 204OAI3A . . . . . . . . . . . . . . . . . . . . . . . . . . 205OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207OR2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 207OR2B . . . . . . . . . . . . . . . . . . . . . . . . . . . 208OR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208OR3A . . . . . . . . . . . . . . . . . . . . . . . . . . . 209OR3B . . . . . . . . . . . . . . . . . . . . . . . . . . . 209OR3C . . . . . . . . . . . . . . . . . . . . . . . . . . . 210OR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210OR4A . . . . . . . . . . . . . . . . . . . . . . . . . . . 211OR4B . . . . . . . . . . . . . . . . . . . . . . . . . . . 211OR4C . . . . . . . . . . . . . . . . . . . . . . . . . . . 212OR4D . . . . . . . . . . . . . . . . . . . . . . . . . . . 212OR5A . . . . . . . . . . . . . . . . . . . . . . . . . . . 213OR5B . . . . . . . . . . . . . . . . . . . . . . . . . . . 213OR5C . . . . . . . . . . . . . . . . . . . . . . . . . . . 214QCLKINT . . . . . . . . . . . . . . . . . . . . . . . . 214QCLKINTI . . . . . . . . . . . . . . . . . . . . . . . . 215TF1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 215TF1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 216VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216XA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

XA1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 217XA1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 218XA1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 218XAI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219XAI1A . . . . . . . . . . . . . . . . . . . . . . . . . . 219XNOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 220XNOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . 220XO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221XO1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 221XOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 222XOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 222XOR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 223XNOR4 . . . . . . . . . . . . . . . . . . . . . . . . . . 224ZOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 225ZOR3I . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

List of Sequential Macros

DF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89DF1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90DF1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90DF1C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91DFC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91DFC1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 92DFC1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 92DFC1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 93DFC1D . . . . . . . . . . . . . . . . . . . . . . . . . . . 93DFC1E . . . . . . . . . . . . . . . . . . . . . . . . . . . 94DFC1F . . . . . . . . . . . . . . . . . . . . . . . . . . . 94DFC1G . . . . . . . . . . . . . . . . . . . . . . . . . . . 95DFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95DFE1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 96DFE1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 96DFE2D . . . . . . . . . . . . . . . . . . . . . . . . . . . 97DFE3A . . . . . . . . . . . . . . . . . . . . . . . . . . . 97DFE3B . . . . . . . . . . . . . . . . . . . . . . . . . . . 98DFE3C . . . . . . . . . . . . . . . . . . . . . . . . . . . 98DFE3D . . . . . . . . . . . . . . . . . . . . . . . . . . . 99DFE4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99DFE4A . . . . . . . . . . . . . . . . . . . . . . . . . . 100DFE4B . . . . . . . . . . . . . . . . . . . . . . . . . . 100DFE4C . . . . . . . . . . . . . . . . . . . . . . . . . . 101DFE4F . . . . . . . . . . . . . . . . . . . . . . . . . . 101DFE4G . . . . . . . . . . . . . . . . . . . . . . . . . . 102DFEA . . . . . . . . . . . . . . . . . . . . . . . . . . . 102DFEB . . . . . . . . . . . . . . . . . . . . . . . . . . . 103DFEC . . . . . . . . . . . . . . . . . . . . . . . . . . . 103DFED . . . . . . . . . . . . . . . . . . . . . . . . . . . 104DFEG . . . . . . . . . . . . . . . . . . . . . . . . . . . 104DFEH . . . . . . . . . . . . . . . . . . . . . . . . . . . 105IODFE . . . . . . . . . . . . . . . . . . . . . . . . . . 105IODFEC . . . . . . . . . . . . . . . . . . . . . . . . . 106IODFEP . . . . . . . . . . . . . . . . . . . . . . . . . 106DFM . . . . . . . . . . . . . . . . . . . . . . . . . . . 107DFMEG . . . . . . . . . . . . . . . . . . . . . . . . . 107DFMEH . . . . . . . . . . . . . . . . . . . . . . . . . 108

DFM1B . . . . . . . . . . . . . . . . . . . . . . . . . 108DFM1C . . . . . . . . . . . . . . . . . . . . . . . . . 109DFM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 109DFM3B . . . . . . . . . . . . . . . . . . . . . . . . . 110DFM3E . . . . . . . . . . . . . . . . . . . . . . . . . . 110DFM3F . . . . . . . . . . . . . . . . . . . . . . . . . . 111DFM3G . . . . . . . . . . . . . . . . . . . . . . . . . 111DFM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 112DFM4A . . . . . . . . . . . . . . . . . . . . . . . . . 112DFM4B . . . . . . . . . . . . . . . . . . . . . . . . . 113DFM4C . . . . . . . . . . . . . . . . . . . . . . . . . 113DFM4D . . . . . . . . . . . . . . . . . . . . . . . . . 114DFM4E . . . . . . . . . . . . . . . . . . . . . . . . . . 114DFM5A . . . . . . . . . . . . . . . . . . . . . . . . . 115DFM5B . . . . . . . . . . . . . . . . . . . . . . . . . 115DFM6A . . . . . . . . . . . . . . . . . . . . . . . . . 116DFM6B . . . . . . . . . . . . . . . . . . . . . . . . . 116DFM7A . . . . . . . . . . . . . . . . . . . . . . . . . 117DFM7B . . . . . . . . . . . . . . . . . . . . . . . . . 118DFM8A . . . . . . . . . . . . . . . . . . . . . . . . . 119DFM8B . . . . . . . . . . . . . . . . . . . . . . . . . 120DFMA . . . . . . . . . . . . . . . . . . . . . . . . . . 121DFMB . . . . . . . . . . . . . . . . . . . . . . . . . . 121DFME1A . . . . . . . . . . . . . . . . . . . . . . . . 122DFME1B . . . . . . . . . . . . . . . . . . . . . . . . 122DFME2A . . . . . . . . . . . . . . . . . . . . . . . . 123DFME2B . . . . . . . . . . . . . . . . . . . . . . . . 123DFME3A . . . . . . . . . . . . . . . . . . . . . . . . 124DFME3B . . . . . . . . . . . . . . . . . . . . . . . . 124DFMPCA . . . . . . . . . . . . . . . . . . . . . . . . 125DFMPCB . . . . . . . . . . . . . . . . . . . . . . . . 125DFP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 126DFP1A . . . . . . . . . . . . . . . . . . . . . . . . . . 126DFP1B . . . . . . . . . . . . . . . . . . . . . . . . . . 127DFP1C . . . . . . . . . . . . . . . . . . . . . . . . . . 127DFP1D . . . . . . . . . . . . . . . . . . . . . . . . . . 128DFP1E . . . . . . . . . . . . . . . . . . . . . . . . . . 128DFP1F . . . . . . . . . . . . . . . . . . . . . . . . . . 129

List of Sequential Macros

DFP1G . . . . . . . . . . . . . . . . . . . . . . . . . . 129DFPC . . . . . . . . . . . . . . . . . . . . . . . . . . . 130DFPCA . . . . . . . . . . . . . . . . . . . . . . . . . . 130DFPCB . . . . . . . . . . . . . . . . . . . . . . . . . . 131DFPCC . . . . . . . . . . . . . . . . . . . . . . . . . . 131DL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132DL1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 132DL1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 133DL1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 133DL2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 134DL2B . . . . . . . . . . . . . . . . . . . . . . . . . . . 134DL2C . . . . . . . . . . . . . . . . . . . . . . . . . . . 135DL2D . . . . . . . . . . . . . . . . . . . . . . . . . . . 136DLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136DLC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 137DLC1A . . . . . . . . . . . . . . . . . . . . . . . . . . 137DLC1F . . . . . . . . . . . . . . . . . . . . . . . . . . 138DLC1G . . . . . . . . . . . . . . . . . . . . . . . . . . 138DLCA . . . . . . . . . . . . . . . . . . . . . . . . . . . 139DLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139DLE1D . . . . . . . . . . . . . . . . . . . . . . . . . . 140DLE2A . . . . . . . . . . . . . . . . . . . . . . . . . . 140DLE2B . . . . . . . . . . . . . . . . . . . . . . . . . . 141DLE2C . . . . . . . . . . . . . . . . . . . . . . . . . . 141DLE3A . . . . . . . . . . . . . . . . . . . . . . . . . . 142DLE3B . . . . . . . . . . . . . . . . . . . . . . . . . . 142DLE3C . . . . . . . . . . . . . . . . . . . . . . . . . . 143DLEA . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

DF1_CC . . . . . . . . . . . . . . . . . . . . . . . . . 228DF1A_CC . . . . . . . . . . . . . . . . . . . . . . . . 228DF1B_CC . . . . . . . . . . . . . . . . . . . . . . . . 229DF1C_CC . . . . . . . . . . . . . . . . . . . . . . . . 229DFC1_CC . . . . . . . . . . . . . . . . . . . . . . . . 230DFC1A_CC . . . . . . . . . . . . . . . . . . . . . . . 230DFC1B_CC . . . . . . . . . . . . . . . . . . . . . . . 231DFC1D_CC . . . . . . . . . . . . . . . . . . . . . . . 231DFE_CC . . . . . . . . . . . . . . . . . . . . . . . . . 232DFE1B_CC . . . . . . . . . . . . . . . . . . . . . . . 232DFE1C_CC . . . . . . . . . . . . . . . . . . . . . . . 233DFEA_CC . . . . . . . . . . . . . . . . . . . . . . . . 233DFM_CC . . . . . . . . . . . . . . . . . . . . . . . . . 234DFMA_CC . . . . . . . . . . . . . . . . . . . . . . . 234DFM1B_CC. . . . . . . . . . . . . . . . . . . . . . . 235DFM1C_CC. . . . . . . . . . . . . . . . . . . . . . . 235DFP1_CC* . . . . . . . . . . . . . . . . . . . . . . . 236DFP1A_CC* . . . . . . . . . . . . . . . . . . . . . . 236DFP1B_CC* . . . . . . . . . . . . . . . . . . . . . . 237DFP1D_CC* . . . . . . . . . . . . . . . . . . . . . . 237DFPC_CC* . . . . . . . . . . . . . . . . . . . . . . . 238DFPCA_CC* . . . . . . . . . . . . . . . . . . . . . . 238

List of CC Macros

RAM4FA . . . . . . . . . . . . . . . . . . . . . . . . 240RAM4FF . . . . . . . . . . . . . . . . . . . . . . . . . 241RAM4FR. . . . . . . . . . . . . . . . . . . . . . . . . 242RAM4RA . . . . . . . . . . . . . . . . . . . . . . . . 243RAM4RF. . . . . . . . . . . . . . . . . . . . . . . . . 244RAM4RR . . . . . . . . . . . . . . . . . . . . . . . . 245RAM8FA . . . . . . . . . . . . . . . . . . . . . . . . 246RAM8FF . . . . . . . . . . . . . . . . . . . . . . . . . 247RAM8FR. . . . . . . . . . . . . . . . . . . . . . . . . 248RAM8RA . . . . . . . . . . . . . . . . . . . . . . . . 249RAM8RF. . . . . . . . . . . . . . . . . . . . . . . . . 250RAM8RR . . . . . . . . . . . . . . . . . . . . . . . . 251RAM64K36 /RAM64K36P . . . . . . . . . . . 252FIFO64K36/FIFO64K36P . . . . . . . . . . . . 253

List of RAM Macros

List of Input/Output Macros

BIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . 256CLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . 256HCLKBIBUF . . . . . . . . . . . . . . . . . . . . . . 257CLKBIBUFI . . . . . . . . . . . . . . . . . . . . . . . 257CLKBUF . . . . . . . . . . . . . . . . . . . . . . . . . 258CLKBUFI . . . . . . . . . . . . . . . . . . . . . . . . 258HCLKBUF . . . . . . . . . . . . . . . . . . . . . . . 259INBUF . . . . . . . . . . . . . . . . . . . . . . . . . . 259OUTBUF . . . . . . . . . . . . . . . . . . . . . . . . 260QCLKBIBUFI . . . . . . . . . . . . . . . . . . . . . 261QCLKBIBUF . . . . . . . . . . . . . . . . . . . . . . 261QCLKBUF . . . . . . . . . . . . . . . . . . . . . . . 262QCLKBUFI . . . . . . . . . . . . . . . . . . . . . . . 262TRIBUFF . . . . . . . . . . . . . . . . . . . . . . . . 263BBDLHS . . . . . . . . . . . . . . . . . . . . . . . . . 264BBHS . . . . . . . . . . . . . . . . . . . . . . . . . . . 264IBDL . . . . . . . . . . . . . . . . . . . . . . . . . . . 265IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265IRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266OBDLHS . . . . . . . . . . . . . . . . . . . . . . . . 266OBHS . . . . . . . . . . . . . . . . . . . . . . . . . . . 267ORH . . . . . . . . . . . . . . . . . . . . . . . . . . . 267ORIH . . . . . . . . . . . . . . . . . . . . . . . . . . . 268ORITH . . . . . . . . . . . . . . . . . . . . . . . . . . 268ORTH . . . . . . . . . . . . . . . . . . . . . . . . . . 269TBDLHS . . . . . . . . . . . . . . . . . . . . . . . . . 270TBHS . . . . . . . . . . . . . . . . . . . . . . . . . . . 270BBHSA . . . . . . . . . . . . . . . . . . . . . . . . . . 271BBLSA . . . . . . . . . . . . . . . . . . . . . . . . . . 271BBUFTH . . . . . . . . . . . . . . . . . . . . . . . . . 272BBUFTL . . . . . . . . . . . . . . . . . . . . . . . . . 272BIECTH . . . . . . . . . . . . . . . . . . . . . . . . . 273BIECTL . . . . . . . . . . . . . . . . . . . . . . . . . . 273BIEPTH . . . . . . . . . . . . . . . . . . . . . . . . . 274BIEPTL . . . . . . . . . . . . . . . . . . . . . . . . . . 274BRECTH . . . . . . . . . . . . . . . . . . . . . . . . . 275BRECTL . . . . . . . . . . . . . . . . . . . . . . . . . 275BREPTH . . . . . . . . . . . . . . . . . . . . . . . . . 276

BREPTL . . . . . . . . . . . . . . . . . . . . . . . . . 276DECETH . . . . . . . . . . . . . . . . . . . . . . . . . 277DECETL . . . . . . . . . . . . . . . . . . . . . . . . . 277DEPETH . . . . . . . . . . . . . . . . . . . . . . . . . 278DEPETL . . . . . . . . . . . . . . . . . . . . . . . . . 278FECTH . . . . . . . . . . . . . . . . . . . . . . . . . . 279FECTL . . . . . . . . . . . . . . . . . . . . . . . . . . . 279FEPTH . . . . . . . . . . . . . . . . . . . . . . . . . . 280FEPTL . . . . . . . . . . . . . . . . . . . . . . . . . . . 280FECTMH . . . . . . . . . . . . . . . . . . . . . . . . 281FECTML . . . . . . . . . . . . . . . . . . . . . . . . . 281FEPTMH . . . . . . . . . . . . . . . . . . . . . . . . . 282FEPTML . . . . . . . . . . . . . . . . . . . . . . . . . 282IBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283IOCLKBUF . . . . . . . . . . . . . . . . . . . . . . . 283IOPCLBUF . . . . . . . . . . . . . . . . . . . . . . . 284IREC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284IREP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285OBUFTH . . . . . . . . . . . . . . . . . . . . . . . . 285OBUFTL . . . . . . . . . . . . . . . . . . . . . . . . . 286ORECTH . . . . . . . . . . . . . . . . . . . . . . . . . 286ORECTL . . . . . . . . . . . . . . . . . . . . . . . . . 287OREPTH . . . . . . . . . . . . . . . . . . . . . . . . . 287OREPTL . . . . . . . . . . . . . . . . . . . . . . . . . 288INBUF_X . . . . . . . . . . . . . . . . . . . . . . . . 289BIBUF_X . . . . . . . . . . . . . . . . . . . . . . . . 291CLKBUF_X . . . . . . . . . . . . . . . . . . . . . . . 293HCLKBUF_X . . . . . . . . . . . . . . . . . . . . . . 294OUTBUF_X . . . . . . . . . . . . . . . . . . . . . . 295TRIBUFF_X . . . . . . . . . . . . . . . . . . . . . . . 296INBUF_LVDS; INBUF_LVPECL . . . . . . . . 298CLKBUF_LVDS; CLKBUF_LVPECL . . . . . 298HCLKBUF_LVDS; HCLKBUF_LVPECL . . . 299OUTBUF_LVDS; OUTBUF_LVPECL . . . . 299DDR_REG macro . . . . . . . . . . . . . . . . . . 300ADD1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 302SUB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 302ADDSUB1 . . . . . . . . . . . . . . . . . . . . . . . 303

List of Input/Output Macros

MULT1 . . . . . . . . . . . . . . . . . . . . . . . . . . 304ARCNTECP1 . . . . . . . . . . . . . . . . . . . . . . 305AFCNTECP1 . . . . . . . . . . . . . . . . . . . . . . 305SRCNTECP1 . . . . . . . . . . . . . . . . . . . . . . 306SFCNTECP1 . . . . . . . . . . . . . . . . . . . . . . 306ARCNTELDCP1 . . . . . . . . . . . . . . . . . . . 307AFCNTELDCP1 . . . . . . . . . . . . . . . . . . . . 308SRCNTELDCP1 . . . . . . . . . . . . . . . . . . . . 308SFCNTELDCP1 . . . . . . . . . . . . . . . . . . . . 309FCEND_BUFF . . . . . . . . . . . . . . . . . . . . . 309FCEND_INV . . . . . . . . . . . . . . . . . . . . . . 310FCINIT_BUFF . . . . . . . . . . . . . . . . . . . . . 310FCINIT_GND . . . . . . . . . . . . . . . . . . . . . 311FCINIT_INV . . . . . . . . . . . . . . . . . . . . . . 311FCINIT_VCC . . . . . . . . . . . . . . . . . . . . . . 312PLL; PLLFB . . . . . . . . . . . . . . . . . . . . . . . 314PLLINT . . . . . . . . . . . . . . . . . . . . . . . . . . 315PLLOUT . . . . . . . . . . . . . . . . . . . . . . . . . 315PLLHCLK . . . . . . . . . . . . . . . . . . . . . . . . 316PLLRCLK . . . . . . . . . . . . . . . . . . . . . . . . 316

Alphabetical List of Macros

A01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36ADD1 . . . . . . . . . . . . . . . . . . . . . . . . . . 302ADDSUB1 . . . . . . . . . . . . . . . . . . . . . . . 303AFCNTECP1 . . . . . . . . . . . . . . . . . . . . . . 305AFCNTELDCP1 . . . . . . . . . . . . . . . . . . . 308AND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29AND2A. . . . . . . . . . . . . . . . . . . . . . . . . . . 29AND2B . . . . . . . . . . . . . . . . . . . . . . . . . . . 30AND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30AND3A. . . . . . . . . . . . . . . . . . . . . . . . . . . 31AND3B . . . . . . . . . . . . . . . . . . . . . . . . . . . 31AND3C . . . . . . . . . . . . . . . . . . . . . . . . . . . 32AND4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32AND4A. . . . . . . . . . . . . . . . . . . . . . . . . . . 33AND4B . . . . . . . . . . . . . . . . . . . . . . . . . . . 33AND4C . . . . . . . . . . . . . . . . . . . . . . . . . . . 34AND4D. . . . . . . . . . . . . . . . . . . . . . . . . . . 34AND5A. . . . . . . . . . . . . . . . . . . . . . . . . . . 35AND5B . . . . . . . . . . . . . . . . . . . . . . . . . . . 35AND5C . . . . . . . . . . . . . . . . . . . . . . . . . . . 36AO10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37AO11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37AO12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38AO13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38AO14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39AO15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39AO16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40AO17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40AO18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41AO1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41AO1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42AO1C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42AO1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43AO1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43AO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44AO2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44AO2B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45AO2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

AO2D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46AO2E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46AO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47AO3A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47AO3B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48AO3C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48AO4A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49AO5A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49AO6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50AO6A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50AO7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51AO8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51AO9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52AOI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52AOI1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 53AOI1B. . . . . . . . . . . . . . . . . . . . . . . . . . . . 53AOI1C. . . . . . . . . . . . . . . . . . . . . . . . . . . . 54AOI1D . . . . . . . . . . . . . . . . . . . . . . . . . . . 54AOI2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 55AOI2B. . . . . . . . . . . . . . . . . . . . . . . . . . . . 55AOI3A . . . . . . . . . . . . . . . . . . . . . . . . . . . 56AOI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56AOI4A . . . . . . . . . . . . . . . . . . . . . . . . . . . 57AOI5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57ARCNTECP1 . . . . . . . . . . . . . . . . . . . . . . 305ARCNTELDCP1 . . . . . . . . . . . . . . . . . . . 307AX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58AX1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58AX1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59AX1C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59AX1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60AX1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60AXO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61AXO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61AXO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62AXO5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62AXO6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63AXO7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

AXOI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 64AXOI2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 64AXOI3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 65AXOI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 65AXOI5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 66AXOI7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 66BBDLHS . . . . . . . . . . . . . . . . . . . . . . . . . 264BBHS . . . . . . . . . . . . . . . . . . . . . . . . . . . 264BBHSA . . . . . . . . . . . . . . . . . . . . . . . . . . 271BBLSA . . . . . . . . . . . . . . . . . . . . . . . . . . 271BBUFTH . . . . . . . . . . . . . . . . . . . . . . . . . 272BBUFTL . . . . . . . . . . . . . . . . . . . . . . . . . 272BIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . 256BIBUF_X . . . . . . . . . . . . . . . . . . . . . . . . 291BIECTH . . . . . . . . . . . . . . . . . . . . . . . . . 273BIECTL . . . . . . . . . . . . . . . . . . . . . . . . . . 273BIEPTH . . . . . . . . . . . . . . . . . . . . . . . . . 274BIEPTL . . . . . . . . . . . . . . . . . . . . . . . . . . 274BRECTH . . . . . . . . . . . . . . . . . . . . . . . . . 275BRECTL . . . . . . . . . . . . . . . . . . . . . . . . . 275BREPTH . . . . . . . . . . . . . . . . . . . . . . . . . 276BREPTL . . . . . . . . . . . . . . . . . . . . . . . . . 276BUFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67BUFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68BUFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67CLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . 256CLKBIBUFI . . . . . . . . . . . . . . . . . . . . . . . 257CLKBUF . . . . . . . . . . . . . . . . . . . . . . . . . 258CLKBUF_LVDS; CLKBUF_LVPECL . . . . . 298CLKBUF_X . . . . . . . . . . . . . . . . . . . . . . . 293CLKBUFI . . . . . . . . . . . . . . . . . . . . . . . . 258CLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . . 68CLKINTI . . . . . . . . . . . . . . . . . . . . . . . . . . 69CM7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70CM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71CM8A. . . . . . . . . . . . . . . . . . . . . . . . . . . . 72CM8F . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73CM8INV . . . . . . . . . . . . . . . . . . . . . . . . . . 74CMA9. . . . . . . . . . . . . . . . . . . . . . . . . . . . 74CMAF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75CMB3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75CMB7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76CMBB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

CMBF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77CMEA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77CMEB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78CMEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78CMEF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79CMF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79CMF2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80CMF3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80CMF4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81CMF5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81CMF6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82CMF7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82CMF8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83CMF9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83CMFA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84CMFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84CMFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85CMFD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85CMFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86CS1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86CS2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87CY2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87CY2B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89DDR_REG macro . . . . . . . . . . . . . . . . . . 300DECETH . . . . . . . . . . . . . . . . . . . . . . . . . 277DECETL . . . . . . . . . . . . . . . . . . . . . . . . . 277DEPETH . . . . . . . . . . . . . . . . . . . . . . . . . 278DEPETL . . . . . . . . . . . . . . . . . . . . . . . . . 278DF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89DF1_CC . . . . . . . . . . . . . . . . . . . . . . . . . 228DF1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90DF1A_CC . . . . . . . . . . . . . . . . . . . . . . . . 228DF1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90DF1B_CC . . . . . . . . . . . . . . . . . . . . . . . . 229DF1C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91DF1C_CC . . . . . . . . . . . . . . . . . . . . . . . . 229DFC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91DFC1_CC . . . . . . . . . . . . . . . . . . . . . . . . 230DFC1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 92DFC1A_CC . . . . . . . . . . . . . . . . . . . . . . . 230DFC1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 92DFC1B_CC . . . . . . . . . . . . . . . . . . . . . . . 231DFC1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

DFC1D . . . . . . . . . . . . . . . . . . . . . . . . . . . 93DFC1D_CC . . . . . . . . . . . . . . . . . . . . . . . 231DFC1E . . . . . . . . . . . . . . . . . . . . . . . . . . . 94DFC1F . . . . . . . . . . . . . . . . . . . . . . . . . . . 94DFC1G . . . . . . . . . . . . . . . . . . . . . . . . . . . 95DFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95DFE_CC . . . . . . . . . . . . . . . . . . . . . . . . . 232DFE1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 96DFE1B_CC . . . . . . . . . . . . . . . . . . . . . . . 232DFE1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 96DFE1C_CC . . . . . . . . . . . . . . . . . . . . . . . 233DFE2D . . . . . . . . . . . . . . . . . . . . . . . . . . . 97DFE3A . . . . . . . . . . . . . . . . . . . . . . . . . . . 97DFE3B . . . . . . . . . . . . . . . . . . . . . . . . . . . 98DFE3C . . . . . . . . . . . . . . . . . . . . . . . . . . . 98DFE3D . . . . . . . . . . . . . . . . . . . . . . . . . . . 99DFE4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99DFE4A . . . . . . . . . . . . . . . . . . . . . . . . . . 100DFE4B . . . . . . . . . . . . . . . . . . . . . . . . . . 100DFE4C . . . . . . . . . . . . . . . . . . . . . . . . . . 101DFE4F . . . . . . . . . . . . . . . . . . . . . . . . . . 101DFE4G . . . . . . . . . . . . . . . . . . . . . . . . . . 102DFEA . . . . . . . . . . . . . . . . . . . . . . . . . . . 102DFEA_CC . . . . . . . . . . . . . . . . . . . . . . . . 233DFEB . . . . . . . . . . . . . . . . . . . . . . . . . . . 103DFEC . . . . . . . . . . . . . . . . . . . . . . . . . . . 103DFED . . . . . . . . . . . . . . . . . . . . . . . . . . . 104DFEG . . . . . . . . . . . . . . . . . . . . . . . . . . . 104DFEH . . . . . . . . . . . . . . . . . . . . . . . . . . . 105DFM . . . . . . . . . . . . . . . . . . . . . . . . . . . 107DFM_CC . . . . . . . . . . . . . . . . . . . . . . . . 234DFM1B . . . . . . . . . . . . . . . . . . . . . . . . . 108DFM1B_CC . . . . . . . . . . . . . . . . . . . . . . 235DFM1C . . . . . . . . . . . . . . . . . . . . . . . . . 109DFM1C_CC . . . . . . . . . . . . . . . . . . . . . . 235DFM3 . . . . . . . . . . . . . . . . . . . . . . . . . . 109DFM3B . . . . . . . . . . . . . . . . . . . . . . . . . 110DFM3E . . . . . . . . . . . . . . . . . . . . . . . . . 110DFM3F . . . . . . . . . . . . . . . . . . . . . . . . . 111DFM3G . . . . . . . . . . . . . . . . . . . . . . . . . 111DFM4 . . . . . . . . . . . . . . . . . . . . . . . . . . 112DFM4A . . . . . . . . . . . . . . . . . . . . . . . . . 112DFM4B . . . . . . . . . . . . . . . . . . . . . . . . . 113

DFM4C . . . . . . . . . . . . . . . . . . . . . . . . . 113DFM4D . . . . . . . . . . . . . . . . . . . . . . . . . 114DFM4E . . . . . . . . . . . . . . . . . . . . . . . . . . 114DFM5A . . . . . . . . . . . . . . . . . . . . . . . . . 115DFM5B . . . . . . . . . . . . . . . . . . . . . . . . . 115DFM6A . . . . . . . . . . . . . . . . . . . . . . . . . 116DFM6B . . . . . . . . . . . . . . . . . . . . . . . . . 116DFM7A . . . . . . . . . . . . . . . . . . . . . . . . . 117DFM7B . . . . . . . . . . . . . . . . . . . . . . . . . 118DFM8A . . . . . . . . . . . . . . . . . . . . . . . . . 119DFM8B . . . . . . . . . . . . . . . . . . . . . . . . . 120DFMA . . . . . . . . . . . . . . . . . . . . . . . . . . 121DFMA_CC . . . . . . . . . . . . . . . . . . . . . . . 234DFMB . . . . . . . . . . . . . . . . . . . . . . . . . . 121DFME1A . . . . . . . . . . . . . . . . . . . . . . . . 122DFME1B . . . . . . . . . . . . . . . . . . . . . . . . 122DFME2A . . . . . . . . . . . . . . . . . . . . . . . . 123DFME2B . . . . . . . . . . . . . . . . . . . . . . . . 123DFME3A . . . . . . . . . . . . . . . . . . . . . . . . 124DFME3B . . . . . . . . . . . . . . . . . . . . . . . . 124DFMEG . . . . . . . . . . . . . . . . . . . . . . . . . 107DFMEH . . . . . . . . . . . . . . . . . . . . . . . . . 108DFMPCA . . . . . . . . . . . . . . . . . . . . . . . . 125DFMPCB . . . . . . . . . . . . . . . . . . . . . . . . 125DFP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 126DFP1_CC* . . . . . . . . . . . . . . . . . . . . . . . 236DFP1A . . . . . . . . . . . . . . . . . . . . . . . . . . 126DFP1A_CC* . . . . . . . . . . . . . . . . . . . . . . 236DFP1B . . . . . . . . . . . . . . . . . . . . . . . . . . 127DFP1B_CC* . . . . . . . . . . . . . . . . . . . . . . 237DFP1C . . . . . . . . . . . . . . . . . . . . . . . . . . 127DFP1D . . . . . . . . . . . . . . . . . . . . . . . . . . 128DFP1D_CC* . . . . . . . . . . . . . . . . . . . . . . 237DFP1E . . . . . . . . . . . . . . . . . . . . . . . . . . 128DFP1F . . . . . . . . . . . . . . . . . . . . . . . . . . 129DFP1G . . . . . . . . . . . . . . . . . . . . . . . . . . 129DFPC . . . . . . . . . . . . . . . . . . . . . . . . . . . 130DFPC_CC* . . . . . . . . . . . . . . . . . . . . . . . 238DFPCA . . . . . . . . . . . . . . . . . . . . . . . . . . 130DFPCA_CC* . . . . . . . . . . . . . . . . . . . . . . 238DFPCB . . . . . . . . . . . . . . . . . . . . . . . . . . 131DFPCC . . . . . . . . . . . . . . . . . . . . . . . . . . 131DL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

DL1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 132DL1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 133DL1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 133DL2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 134DL2B . . . . . . . . . . . . . . . . . . . . . . . . . . . 134DL2C . . . . . . . . . . . . . . . . . . . . . . . . . . . 135DL2D . . . . . . . . . . . . . . . . . . . . . . . . . . . 136DLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136DLC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 137DLC1A . . . . . . . . . . . . . . . . . . . . . . . . . . 137DLC1F . . . . . . . . . . . . . . . . . . . . . . . . . . 138DLC1G . . . . . . . . . . . . . . . . . . . . . . . . . . 138DLCA . . . . . . . . . . . . . . . . . . . . . . . . . . . 139DLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139DLE1D . . . . . . . . . . . . . . . . . . . . . . . . . . 140DLE2A . . . . . . . . . . . . . . . . . . . . . . . . . . 140DLE2B . . . . . . . . . . . . . . . . . . . . . . . . . . 141DLE2C . . . . . . . . . . . . . . . . . . . . . . . . . . 141DLE3A . . . . . . . . . . . . . . . . . . . . . . . . . . 142DLE3B . . . . . . . . . . . . . . . . . . . . . . . . . . 142DLE3C . . . . . . . . . . . . . . . . . . . . . . . . . . 143DLEA . . . . . . . . . . . . . . . . . . . . . . . . . . . 143DLEB . . . . . . . . . . . . . . . . . . . . . . . . . . . 144DLEC . . . . . . . . . . . . . . . . . . . . . . . . . . . 144DLM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145DLM2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 145DLM2A. . . . . . . . . . . . . . . . . . . . . . . . . . 147DLM2B . . . . . . . . . . . . . . . . . . . . . . . . . . 147DLM3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 148DLM3A. . . . . . . . . . . . . . . . . . . . . . . . . . 148DLM4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 149DLM4A. . . . . . . . . . . . . . . . . . . . . . . . . . 149DLM8A. . . . . . . . . . . . . . . . . . . . . . . . . . 150DLM8B . . . . . . . . . . . . . . . . . . . . . . . . . . 151DLMA. . . . . . . . . . . . . . . . . . . . . . . . . . . 152DLME1A. . . . . . . . . . . . . . . . . . . . . . . . . 152DLP1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 153DLP1A . . . . . . . . . . . . . . . . . . . . . . . . . . 153DLP1B . . . . . . . . . . . . . . . . . . . . . . . . . . 154DLP1C . . . . . . . . . . . . . . . . . . . . . . . . . . 154DLP1D . . . . . . . . . . . . . . . . . . . . . . . . . . 155DLP1E. . . . . . . . . . . . . . . . . . . . . . . . . . . 155DXAND7 . . . . . . . . . . . . . . . . . . . . . . . . 156

DXAX7 . . . . . . . . . . . . . . . . . . . . . . . . . . 157DXNAND7 . . . . . . . . . . . . . . . . . . . . . . . 157FA1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158FA1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 158FA1B. . . . . . . . . . . . . . . . . . . . . . . . . . . . 159FA2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 159FCEND_BUFF . . . . . . . . . . . . . . . . . . . . . 309FCEND_INV . . . . . . . . . . . . . . . . . . . . . . 310FCINIT_BUFF . . . . . . . . . . . . . . . . . . . . . 310FCINIT_GND . . . . . . . . . . . . . . . . . . . . . 311FCINIT_INV . . . . . . . . . . . . . . . . . . . . . . 311FCINIT_VCC . . . . . . . . . . . . . . . . . . . . . . 312FECTH . . . . . . . . . . . . . . . . . . . . . . . . . . 279FECTL . . . . . . . . . . . . . . . . . . . . . . . . . . . 279FECTMH . . . . . . . . . . . . . . . . . . . . . . . . 281FECTML . . . . . . . . . . . . . . . . . . . . . . . . . 281FEPTH . . . . . . . . . . . . . . . . . . . . . . . . . . 280FEPTL . . . . . . . . . . . . . . . . . . . . . . . . . . . 280FEPTMH . . . . . . . . . . . . . . . . . . . . . . . . . 282FEPTML . . . . . . . . . . . . . . . . . . . . . . . . . 282FIFO64K36/FIFO64K36P . . . . . . . . . . . . 253GAND2. . . . . . . . . . . . . . . . . . . . . . . . . . 160GMX4. . . . . . . . . . . . . . . . . . . . . . . . . . . 160GNAND2 . . . . . . . . . . . . . . . . . . . . . . . . 161GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161GNOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 162GOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 162GXOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 163HA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163HA1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 164HA1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 164HA1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 165HCLKBIBUF . . . . . . . . . . . . . . . . . . . . . . 257HCLKBUF . . . . . . . . . . . . . . . . . . . . . . . . 259HCLKBUF_LVDS; HCLKBUF_LVPECL . . . 299HCLKBUF_X . . . . . . . . . . . . . . . . . . . . . . 294HCLKINT. . . . . . . . . . . . . . . . . . . . . . . . . . 69IBDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265IBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283INBUF . . . . . . . . . . . . . . . . . . . . . . . . . . 259INBUF_LVDS; INBUF_LVPECL . . . . . . . . 298INBUF_X . . . . . . . . . . . . . . . . . . . . . . . . 289INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165

INVA . . . . . . . . . . . . . . . . . . . . . . . . . . . 166INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . 166IOCLKBUF . . . . . . . . . . . . . . . . . . . . . . . 283IODFE . . . . . . . . . . . . . . . . . . . . . . . . . . 105IODFEC . . . . . . . . . . . . . . . . . . . . . . . . . 106IODFEP . . . . . . . . . . . . . . . . . . . . . . . . . 106IOPCLBUF . . . . . . . . . . . . . . . . . . . . . . . 284IR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265IREC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284IREP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285IRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266JKF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167JKF1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 168JKF2A. . . . . . . . . . . . . . . . . . . . . . . . . . . 168JKF2B . . . . . . . . . . . . . . . . . . . . . . . . . . . 169JKF2C . . . . . . . . . . . . . . . . . . . . . . . . . . . 169JKF2D. . . . . . . . . . . . . . . . . . . . . . . . . . . 170JKF3A. . . . . . . . . . . . . . . . . . . . . . . . . . . 170JKF3B . . . . . . . . . . . . . . . . . . . . . . . . . . . 171JKF3C . . . . . . . . . . . . . . . . . . . . . . . . . . . 171JKF3D. . . . . . . . . . . . . . . . . . . . . . . . . . . 172JKF4B . . . . . . . . . . . . . . . . . . . . . . . . . . . 173JKFPC . . . . . . . . . . . . . . . . . . . . . . . . . . . 173MAJ3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 174MAJ3X . . . . . . . . . . . . . . . . . . . . . . . . . . 174MAJ3XI . . . . . . . . . . . . . . . . . . . . . . . . . 175MIN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 175MIN3X . . . . . . . . . . . . . . . . . . . . . . . . . . 176MIN3XI. . . . . . . . . . . . . . . . . . . . . . . . . . 177MULT1 . . . . . . . . . . . . . . . . . . . . . . . . . 304MX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178MX2A. . . . . . . . . . . . . . . . . . . . . . . . . . . 178MX2B . . . . . . . . . . . . . . . . . . . . . . . . . . . 179MX2C . . . . . . . . . . . . . . . . . . . . . . . . . . . 179MX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180MXC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 180MXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181NAND2. . . . . . . . . . . . . . . . . . . . . . . . . . 181NAND2A . . . . . . . . . . . . . . . . . . . . . . . . 182NAND2B . . . . . . . . . . . . . . . . . . . . . . . . 182NAND3. . . . . . . . . . . . . . . . . . . . . . . . . . 183NAND3A . . . . . . . . . . . . . . . . . . . . . . . . 183NAND3B . . . . . . . . . . . . . . . . . . . . . . . . 184

NAND3C. . . . . . . . . . . . . . . . . . . . . . . . . 184NAND4. . . . . . . . . . . . . . . . . . . . . . . . . . 185NAND4A . . . . . . . . . . . . . . . . . . . . . . . . 185NAND4B. . . . . . . . . . . . . . . . . . . . . . . . . 186NAND4C. . . . . . . . . . . . . . . . . . . . . . . . . 186NAND4D . . . . . . . . . . . . . . . . . . . . . . . . 187NAND5B. . . . . . . . . . . . . . . . . . . . . . . . . 187NAND5C. . . . . . . . . . . . . . . . . . . . . . . . . 188NAND5D . . . . . . . . . . . . . . . . . . . . . . . . 188NOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 189NOR2A . . . . . . . . . . . . . . . . . . . . . . . . . . 189NOR2B . . . . . . . . . . . . . . . . . . . . . . . . . . 190NOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 191NOR3A . . . . . . . . . . . . . . . . . . . . . . . . . . 191NOR3B . . . . . . . . . . . . . . . . . . . . . . . . . . 192NOR3C . . . . . . . . . . . . . . . . . . . . . . . . . . 192NOR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 193NOR4A . . . . . . . . . . . . . . . . . . . . . . . . . . 193NOR4B . . . . . . . . . . . . . . . . . . . . . . . . . . 194NOR4C . . . . . . . . . . . . . . . . . . . . . . . . . . 194NOR4D . . . . . . . . . . . . . . . . . . . . . . . . . . 195NOR5B . . . . . . . . . . . . . . . . . . . . . . . . . . 195NOR5C . . . . . . . . . . . . . . . . . . . . . . . . . . 196NOR5D . . . . . . . . . . . . . . . . . . . . . . . . . . 196OA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197OA1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 198OA1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 198OA1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 199OA2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199OA2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 200OA3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200OA3A . . . . . . . . . . . . . . . . . . . . . . . . . . . 201OA3B . . . . . . . . . . . . . . . . . . . . . . . . . . . 201OA4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202OA4A . . . . . . . . . . . . . . . . . . . . . . . . . . . 202OA5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203OAI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203OAI2A . . . . . . . . . . . . . . . . . . . . . . . . . . 204OAI3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204OAI3A . . . . . . . . . . . . . . . . . . . . . . . . . . 205OBDLHS . . . . . . . . . . . . . . . . . . . . . . . . . 266OBHS . . . . . . . . . . . . . . . . . . . . . . . . . . . 267OBUFTH . . . . . . . . . . . . . . . . . . . . . . . . 285

OBUFTL . . . . . . . . . . . . . . . . . . . . . . . . . 286OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207OR2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 207OR2B . . . . . . . . . . . . . . . . . . . . . . . . . . . 208OR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208OR3A . . . . . . . . . . . . . . . . . . . . . . . . . . . 209OR3B . . . . . . . . . . . . . . . . . . . . . . . . . . . 209OR3C . . . . . . . . . . . . . . . . . . . . . . . . . . . 210OR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210OR4A . . . . . . . . . . . . . . . . . . . . . . . . . . . 211OR4B . . . . . . . . . . . . . . . . . . . . . . . . . . . 211OR4C . . . . . . . . . . . . . . . . . . . . . . . . . . . 212OR4D . . . . . . . . . . . . . . . . . . . . . . . . . . . 212OR5A . . . . . . . . . . . . . . . . . . . . . . . . . . . 213OR5B . . . . . . . . . . . . . . . . . . . . . . . . . . . 213OR5C . . . . . . . . . . . . . . . . . . . . . . . . . . . 214ORECTH . . . . . . . . . . . . . . . . . . . . . . . . 286ORECTL . . . . . . . . . . . . . . . . . . . . . . . . . 287OREPTH . . . . . . . . . . . . . . . . . . . . . . . . 287OREPTL . . . . . . . . . . . . . . . . . . . . . . . . . 288ORH . . . . . . . . . . . . . . . . . . . . . . . . . . . 267ORIH . . . . . . . . . . . . . . . . . . . . . . . . . . . 268ORITH . . . . . . . . . . . . . . . . . . . . . . . . . . 268ORTH . . . . . . . . . . . . . . . . . . . . . . . . . . 269OUTBUF . . . . . . . . . . . . . . . . . . . . . . . . 260OUTBUF_LVDS; OUTBUF_LVPECL . . . . 299OUTBUF_X . . . . . . . . . . . . . . . . . . . . . . 295PLL; PLLFB . . . . . . . . . . . . . . . . . . . . . . . 314PLLHCLK . . . . . . . . . . . . . . . . . . . . . . . . 316PLLINT . . . . . . . . . . . . . . . . . . . . . . . . . . 315PLLOUT . . . . . . . . . . . . . . . . . . . . . . . . . 315PLLRCLK . . . . . . . . . . . . . . . . . . . . . . . . 316QCLKBIBUF . . . . . . . . . . . . . . . . . . . . . . 261QCLKBIBUFI . . . . . . . . . . . . . . . . . . . . . 261QCLKBUF . . . . . . . . . . . . . . . . . . . . . . . 262QCLKBUFI . . . . . . . . . . . . . . . . . . . . . . . 262QCLKINT . . . . . . . . . . . . . . . . . . . . . . . . 214QCLKINTI . . . . . . . . . . . . . . . . . . . . . . . . 215RAM4FA . . . . . . . . . . . . . . . . . . . . . . . . 240RAM4FF . . . . . . . . . . . . . . . . . . . . . . . . 241RAM4FR . . . . . . . . . . . . . . . . . . . . . . . . 242RAM4RA . . . . . . . . . . . . . . . . . . . . . . . . 243RAM4RF . . . . . . . . . . . . . . . . . . . . . . . . 244

RAM4RR . . . . . . . . . . . . . . . . . . . . . . . . 245RAM64K36 /RAM64K36P . . . . . . . . . . . 252RAM8FA . . . . . . . . . . . . . . . . . . . . . . . . 246RAM8FF . . . . . . . . . . . . . . . . . . . . . . . . . 247RAM8FR . . . . . . . . . . . . . . . . . . . . . . . . 248RAM8RA . . . . . . . . . . . . . . . . . . . . . . . . 249RAM8RF . . . . . . . . . . . . . . . . . . . . . . . . 250RAM8RR . . . . . . . . . . . . . . . . . . . . . . . . 251SFCNTECP1 . . . . . . . . . . . . . . . . . . . . . . 306SFCNTELDCP1 . . . . . . . . . . . . . . . . . . . . 309SRCNTECP1 . . . . . . . . . . . . . . . . . . . . . . 306SRCNTELDCP1 . . . . . . . . . . . . . . . . . . . . 308SUB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 302TBDLHS . . . . . . . . . . . . . . . . . . . . . . . . . 270TBHS . . . . . . . . . . . . . . . . . . . . . . . . . . . 270TF1A. . . . . . . . . . . . . . . . . . . . . . . . . . . . 215TF1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216TRIBUFF . . . . . . . . . . . . . . . . . . . . . . . . . 263TRIBUFF_X . . . . . . . . . . . . . . . . . . . . . . . 296VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216XA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217XA1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 217XA1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 218XA1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 218XAI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219XAI1A. . . . . . . . . . . . . . . . . . . . . . . . . . . 219XNOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . 220XNOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . 220XNOR4 . . . . . . . . . . . . . . . . . . . . . . . . . . 224XO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221XO1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 221XOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 222XOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 222XOR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 223ZOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 225ZOR3I . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Macro Library Guide 27

Combinational/SequentialMacros

Combinational, AND

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input AND

Truth Table A B Y

Function

ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Axcelerator

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input AND with active low A Input

Truth Table A B Y

Function

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input AND with active low Inputs

Truth TableA B Y

Function

A, B,C Y

FamilyModules

Seq Comb

Input Output

3-Input AND

Truth Table A B C Y

X X 0 0

X 0 X 0

0 X X 0

1 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input AND with active low A-Input

Truth TableA B C Y

X X 0 0

X 0 X 0

0 1 1 1

1 X X 0

Function

A, B,C Y

FamilyModules

Seq Comb

Input Output

3-Input AND with active low A- and B-Inputs

Truth Table A B C Y

X X 0 0

0 0 1 1

X 1 X 0

1 X X 0

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

Truth Table A B C Y

0 0 0 1

X X 1 0

X 1 X 0

1 X X 0

Function

A, B, C, D Y

* A 2 on the symbol implies 2 logic module delays, only for ACT 1 and MX.

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

4-Input AND

Truth Table A B C D Y

X X X 0 0

X X 0 X 0

X 0 X X 0

0 X X X 0

1 1 1 1 1

Function

A, B, C, D Y

* A 2 on the symbol implies 2 logic module delays, only for ACT 1 and MX.

FamilyModules

Seq Comb

MX/ACT1 2

Others 1

Input Output

4-Input AND with active low A-Input

X X X 0 0

X X 0 X 0

X 0 X X 0

0 1 1 1 1

1 X X X 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input AND with active low A- and B-Inputs

X X X 0 0

X X 0 X 0

0 0 1 1 1

X 1 X X 0

1 X X X 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input AND with active low A-, B-, and C-Inputs

X X X 0 0

0 0 0 1 1

X X 1 X 0

X 1 X X 0

1 X X X 0

Function

A, B, C, D Y

* A 2 on the symbol implies 2 logic module delays, except SX, SX-A, and eX.

FamilyModules

Seq Comb

SX, SX-A, eX 1

Others 2

Input Output

0 0 0 0 1

X X X 1 0

X X 1 X 0

X 1 X X 0

1 X X X 0

Function

A, B, C, D, E Y

FamilyModules

Seq Comb

All listed 1

Input Output

5-Input AND with active low A input

Truth Table A B C D E Y

0 1 1 1 1 1

1 X X X X 0

X 0 X X X 0

X X 0 X X 0

X X X 0 X 0

X X X X 0 0

Function

SX, SX-A, SX-S, eX, Axcelerator

A, B, C, D, E Y

FamilyModules

Seq Comb

Input Output

5-Input AND with active low A-, and B-Inputs

X X X X 0 0

X X X 0 X 0

X X 0 X X 0

0 0 1 1 1 1

X 1 X X X 0

1 X X X X 0

Function

ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Axcelerator

Combinational

A, B, C, D, E Y

FamilyModules

Seq Comb

SX, SX-A, eX, Axcelerator 1

Input Output

5-Input AND with active low A-, B- and C-Inputs

0 0 0 1 1 1

1 X X X X 0

X 1 X X X 0

X X 1 X X 0

X X X 0 X 0

X X X X 0 0

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input AND-OR

Truth Table A B C Y

X 0 0 0

X X 1 1

0 X 0 0

1 1 X 1

Function

ACT1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Axcelerator

Combinational, AND-OR

A, B, C, D, E Y

FamilyModules

Seq Comb

All except ACT1 and MX 1

Input Output

5-Input AND-OR-AND

X X X 0 0 0

X 0 0 X X 0

X X 1 X 1 1

X X 1 1 X 1

0 X 0 X X 0

1 1 X X 1 1

1 1 X 1 X 1

Function

A, B, C Y

FamilyModules

Seq Comb

All except ACT1 and MX 1

Input Output

3-Input AND-OR

Truth Table A B C Y

X 0 0 0

0 0 X 0

0 X 0 0

X 1 1 1

1 X 1 1

1 1 X 1

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-OR

Truth Table A B C Y

0 0 0 1

1 0 0 0

0 1 0 1

1 1 0 1

0 0 1 0

1 0 1 1

0 1 1 1

1 1 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-OR

Truth Table A B C Y

0 0 0 0

1 0 0 1

0 1 0 1

1 1 0 1

0 0 1 0

1 0 1 0

0 1 1 0

1 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-OR

Truth Table A B C Y

0 0 0 0

1 0 0 1

0 1 0 1

1 1 0 1

0 0 1 1

1 0 1 0

0 1 1 0

1 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-OR

Truth Table A B C Y

0 0 0 1

1 0 0 0

0 1 0 0

1 1 0 0

0 0 1 0

1 0 1 1

0 1 1 1

1 1 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-OR

Truth Table A B C Y

0 0 0 0

1 0 0 0

0 1 0 0

1 1 0 1

0 0 1 1

1 0 1 0

0 1 1 0

1 1 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-OR

Truth Table A B C Y

0 0 0 0

1 0 0 0

0 1 0 1

1 1 0 0

0 0 1 1

1 0 1 0

0 1 1 0

1 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-OR

Truth Table A B C Y

0 0 0 1

1 0 0 0

0 1 0 1

1 1 0 1

0 0 1 0

1 0 1 0

0 1 1 1

1 1 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-OR with active low A-Input

Truth Table A B C Y

X 0 0 0

X X 1 1

0 1 X 1

1 X 0 0

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input AND-OR with active low C-Input

Truth Table A B C Y

X X 0 1

X 0 1 0

0 X 1 0

1 1 X 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input AND-OR with active low A- and C-Inputs

Truth Table A B C Y

X X 0 1

X 0 1 0

0 1 X 1

1 X 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed above 1

Input Output

3-Input AND-OR with active low A- and B-Inputs

Truth Table A B C Y

0 0 X 1

X 1 0 0

X X 1 1

1 X 0 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed above 1

Input Output

3-Input AND-OR with active low Inputs

Truth Table A B C Y

X X 0 1

0 0 X 1

X 1 1 0

1 X 1 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input AND-OR

X 0 0 0 0

X X X 1 1

X X 1 X 1

0 X 0 0 0

1 1 X X 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input AND-OR with active low A-Input

X 0 0 0 0

X X X 1 1

X X 1 X 1

0 1 X X 1

1 X 0 0 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

All listed above 1

Input Output

4-Input AND-OR with active low A and B-Inputs

0 0 X X 1

X 1 0 0 0

X X X 1 1

X X 1 X 1

1 X 0 0 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

All listed above 1

Input Output

4-Input AND-OR with active low A- and C-Inputs

1 X 1 0 0

X 0 1 0 0

0 1 X X 1

X X 0 X 1

X X X 1 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

All listed above 1

Input Output

4-Input AND-OR with active low A-, B- and C-Inputs

X X 0 X 1

0 0 X X 1

X 1 1 0 0

X X X 1 1

1 X 1 0 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

All listed above 1

Input Output

4-Input AND-OR with active low Inputs

X X X 0 1

X X 0 X 1

0 0 X X 1

X 1 1 1 0

1 X 1 1 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input AND-OR with active low A Input

X X 0 0 0

X X X 1 1

X 0 X 0 0

0 1 1 X 1

1 X X 0 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

All listed above 1

Input Output

4-Input AND-OR

X X 0 0 0

X X X 1 1

X 0 X 0 0

0 X X 0 0

1 1 1 X 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

All listed above 1

Input Output

4 Input AND-OR with active low A-, B- Inputs

X X 0 0 0

X X X 1 1

0 0 1 X 1

X 1 X 0 0

1 X X 0 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

All listed above 1

Input Output

4-Input AND-OR with active low A-, B-, C- Inputs

0 0 0 X 1

X X 1 0 0

X X X 1 1

X 1 X 0 0

1 X X 0 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input AND-OR

X X 0 X 0

X 0 X 0 0

0 0 X X 0

0 1 1 X 1

1 X 1 1 1

1 X X 0 0

X 1 1 1 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input AND-OR

X 0 0 0 0

X X X 1 1

0 0 X 0 0

0 1 X X 1

1 X 1 X 1

1 X 0 0 0

X 1 1 X 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

All listed above 1

Input Output

2-wide 4-Inputs AND-OR

X 0 X 0 0

X 0 0 X 0

X X 1 1 1

0 X X 0 0

0 X 0 X 0

1 1 X X 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

All listed above 1

Input Output

2-wide 4-Inputs AND-OR with active low D-Input

X 0 0 X 0

X X 1 0 1

X 0 X 1 0

0 X 0 X 0

0 X X 1 0

1 1 X X 1

Function

A, B, C, D, E Y

FamilyModules

Seq Comb

All listed above 1

Input Output

5-Input AND-OR

X X 0 0 0 0

X X X X 1 1

X X X 1 X 1

X 0 X 0 0 0

0 X X 0 0 0

1 1 1 X X 1

Function

A, B, C, D, E Y

FamilyModules

Seq Comb

All listed above 1

Input Output

5-Input AND-OR with active low C- and D-Inputs

X X 0 0 X 1

X 0 X 1 0 0

X X X X 1 1

X 0 1 X 0 0

0 X X 1 0 0

0 X 1 X 0 0

1 1 X X X 1

Function

A, B, C, D, E Y

FamilyModules

Seq Comb

All listed above 1

Input Output

5-Input AND-OR

X 0 0 0 0 0

X X X X 1 1

X X X 1 X 1

X X 1 X X 1

0 X 0 0 0 0

1 1 X X X 1

Function

A, B, C Y

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1

Input Output

3-Input AND-OR-INVERT

Truth Table A B C Y

X 0 0 1

X X 1 0

0 X 0 1

1 1 X 0

Function

Combinational, AND-OR-INVERT

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input AND-OR-INVERT with active low A-Input

Truth Table A B C Y

X 0 0 1

X X 1 0

0 1 X 0

1 X 0 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input AND-OR-INVERT with active low C-Input

Truth Table A B C Y

X X 0 0

X 0 1 1

0 X 1 1

1 1 X 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed above 1

Input Output

3 Input AND-OR-INVERT with active low A- and B-Inputs

Truth Table A B C Y

0 0 X 0

X 1 0 1

X X 1 0

1 X 0 1

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-OR-INVERT with active low Inputs

Truth Table A B C Y

X X 0 0

0 0 X 0

X 1 1 1

1 X 1 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input AND-OR-INVERT with active low A-Input

X 0 0 0 1

X X X 1 0

X X 1 X 0

0 1 X X 0

1 X 0 0 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input AND-OR-INVERT with active low A- and C-Inputs

X X 0 X 0

X 0 1 0 1

X X X 1 0

0 1 X X 0

1 X 1 0 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input AND-OR-INVERT with active low Inputs

0 X X 0 0

0 0 0 X 0

X X 1 1 1

X 1 X 1 1

1 X X X 1

Function

A, B, C, D Y

* A 2 on the symbol implies 2 logic module delays for all families except SX, SX-A, SX-S, and eX.

FamilyModules

Seq Comb

SX, SX-A, SX-S, eX 1

Others 2

Input Output

2-wide 4-Inputs AND-OR-INVERT

X 0 X 0 1

X 0 0 X 1

X X 1 1 0

0 X X 0 1

0 X 0 X 1

1 1 X X 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

All listed 1

Input Output

2-wide 4-Inputs AND-OR-INVERT with active low C-Input

X 0 X 0 1

X X 0 1 0

X 0 1 X 1

0 X X 0 1

0 X 1 X 1

1 1 X X 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-OR-INVERT

Truth Table A B C Y

0 0 0 1

1 0 0 0

0 1 0 1

1 1 0 1

0 0 1 1

1 0 1 1

0 1 1 0

Function

Combinational, AND-XOR

Combinational, AND-XOR-INVERT

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-XOR with active low A-Input

Truth Table A B C Y

X 0 0 0

X 0 1 1

0 1 0 1

0 1 1 0

1 X 0 0

1 X 1 1

Function

A, B, C Y

* A 2 on the symbol implies 2 logic module delays for all families except ACT 1, MX, SX, SX-A, SX-S and eX.

FamilyModules

Seq Comb

ACT 1,MX,SX, SX-A, SX-S, eX 1

Others 2

Input Output

3-Input AND-XOR-INVERT with active low A-Input

Truth Table A B C Y

X 0 0 1

X 0 1 0

0 1 0 0

0 1 1 1

1 X 0 1

1 X 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input AND-XOR with active low A- and B-Inputs

Truth Table A B C Y

0 0 0 1

0 0 1 0

X 1 0 0

X 1 1 1

1 X 0 0

1 X 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-XOR

Truth Table A B C Y

X 0 0 0

X 0 1 1

0 X 0 0

0 X 1 1

1 1 0 1

1 1 1 0

Function

Combinational, 3-Input Gate

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-XNOR

Truth Table A B C Y

0 0 0 0

1 0 0 1

0 1 0 1

1 1 0 1

0 0 1 1

1 0 1 0

0 1 1 0

1 1 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input AND-XNOR

Truth Table A B C Y

0 0 0 1

1 0 0 1

0 1 0 1

1 1 0 0

0 0 1 0

1 0 1 0

0 1 1 0

1 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

3-Input Combinatorial Gate

Truth Table A B C Y

0 0 0 0

1 0 0 0

0 1 0 1

1 1 0 1

0 0 1 1

1 0 1 1

0 1 1 0

1 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table A B C Y

0 0 0 0

1 0 0 0

0 1 0 1

1 1 0 1

0 0 1 1

1 0 1 1

0 1 1 1

1 1 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table A B C Y

0 0 0 0

1 0 0 1

0 1 0 1

1 1 0 1

0 0 1 1

1 0 1 1

0 1 1 0

1 1 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table A B C Y

0 0 0 1

1 0 0 1

0 1 0 1

1 1 0 0

0 0 1 0

1 0 1 0

0 1 1 1

1 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table A B C Y

0 0 0 1

1 0 0 1

0 1 0 0

1 1 0 0

0 0 1 0

1 0 1 1

0 1 1 1

1 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table A B C Y

0 0 0 1

1 0 0 0

0 1 0 1

1 1 0 1

0 0 1 1

1 0 1 1

0 1 1 0

1 1 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table A B C Y

0 0 0 1

1 0 0 1

0 1 0 0

1 1 0 0

0 0 1 0

1 0 1 0

0 1 1 1

1 1 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table A B C Y

0 0 0 1

1 0 0 1

0 1 0 0

1 1 0 0

0 0 1 0

1 0 1 0

0 1 1 0

1 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table A B C Y

0 0 0 1

1 0 0 0

0 1 0 0

1 1 0 0

0 0 1 0

1 0 1 0

0 1 1 1

1 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table A B C Y

0 0 0 0

1 0 0 0

0 1 0 1

1 1 0 0

0 0 1 1

1 0 1 1

0 1 1 0

1 1 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table A B C Y

0 0 0 0

1 0 0 0

0 1 0 0

1 1 0 1

0 0 1 1

1 0 1 1

0 1 1 0

1 1 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table A B C Y

0 0 0 0

1 0 0 1

0 1 0 0

1 1 0 0

0 0 1 0

1 0 1 0

0 1 1 1

1 1 1 1

Function

Buffers

FamilyModules

Seq Comb

Input Output

Buffer, with active low Input and Output

Truth Table A Y

Function

FamilyModules

Seq Comb

Input Output

Buffer

Truth Table A Y

Function

Clock Interface

FamilyModules

Seq Comb

Input Output

BufferNOTE: The Combiner will not remove this macro

Truth Table A Y

Function

CLKINT

NOTE: CLKINT does not use any modules.For more information on the Global Clock Network, refer to the latest Actel datasheet.

Input Output

Internal Clock Interface

Truth Table A Y

Function

ACT 2, 3200DX, MX, SX, SX-A, SX-S, eX, Axcelerator

HCLKINT

NOTE: CLKINT does not use any modules.For more information on the Global Clock Network, refer to the latest Actel datasheet.

Input Output

Truth Table A Y

Function

Axcelerator

CLKINTI

NOTE: CLKINTI does not use any modules.For more information on the Global Clock Network, refer to Actel’s Databook.

Input Output

Inverting Internal Clock Interface

Truth Table A Y

Function

SX, SX-A, SX-S, eX

Combinational, Module

D0D1D2D3

S0S10S11

Truth Table

S11 S10 S0 Y

0 0 0 D0

0 0 1 D1

X 1 0 D2

1 X 0 D2

X 1 1 D3

1 X 1 D3

FamilyModules

Seq Comb

All listed 1

Input Output

Full Combinational Module

Function

ACT2/1200XL, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Axcelerator

D0, D1, D2, D3, S0, S10, S11

D0D1D2D3

S00S01S10S11

Truth Table

S11 S10 S01 S00 Y

0 0 X 0 D0

0 0 0 X D0

0 0 1 1 D1

X 1 X 0 D2

X 1 0 X D2

1 X X 0 D2

1 X 0 X D2

X 1 1 1 D3

1 X 1 1 D3

FamilyModules

Seq Comb

All listed 1

Input Output

Function

ACT2/1200XL, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Axcelerator

D0, D1, D2, D3, S00, S01, S10, S11

Truth Table S0 S1 SA SB Y

0 0 0 X A0

0 0 1 X A1

1 X X 0 B0

X 1 X 0 B0

1 X X 1 B1

X 1 X 1 B1

FamilyModules

Seq Comb

ACT 1, MX 1

Input Output

Function

ACT 1, MX

A0, A1, B0, B1, SA, SB, S0, S1

S11S10

S01S00

Truth Table S11 S10 S01 S00 Y FY

0 0 X 0 D0 D0

0 0 0 X D0 D0

0 0 1 1 D1 D1

X 1 X 0 D2 D2

X 1 0 X D2 D2

1 X X 0 D2 D2

1 X 0 X D2 D2

X 1 1 1 D3 D3

1 X 1 1 D3 D3

FamilyModules

Seq Comb

All listed 1

Input Output

Full Combinational Module with fast output

Function

D0, D1, D2, D3, S00, S01, S10, S11

CM8INV

NOTE: This macro can drive any number of CM8 pins and will be absorbed into that module.

FamilyModules

Seq Comb

All listed 0

Input Output

Inverter with active low output

Truth TableA Y

Function

S11S01

D0, D3. DB, S01, S11 Y

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D0, D2, D3, DB, S01, S11 Y

FamilyModules

Seq Comb

All listed 1

Input Output

Function

S00S01S11

D0, D1, DB, S00, S01, S11 Y

FamilyModules

Seq Comb

All listed 1

Input Output

S01 S11

Function

S11S01

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D0, D1, D2, DB, S00, S01, S11

S11S01

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D0, D1, D3, DB, S00, S01, S11

D0D1D2D3

S00S01S11

FamilyModules

Seq Comb

All listed 1

Input Output

S01 S11

Function

D0, D1, D2, D3, DB, S00, S01, S11

D1D3DB

S01S10S11

D1, D3, DB, S01, S10, Y S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D0, D1, D3, DB, S01, S10, S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D1, D2, D3, DB, S01, S10, S11

D0D1D2D3

S01S10S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D0, D1, D2, D3, DB, S01, S10, S11

S00S01S10S11

D0, DB, S00, S01, S10, Y S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

S00S01S10S11

D1, DB, S00, S01, S10, Y S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

S01S10S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D0, D1, DB, S00, S01, S10, S11

S00S01S10S11

D2, DB, S00, S01, S10, Y S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

S01S10S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D0, D2, DB, S00, S01, S10, S11

S01S10S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D1, D2, DB, S00, S01, S10, S11

S01S10S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D0, D1, D2, DB, S00, S01, S10, S11

S00S01S10S11

D3, DB, S00, S01, S10, Y S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

S01S10S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D0, D3, DB, S00, S01, S10, S11

S01S10S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D1, D3, DB, S00, S01, S10, S11

S01S10S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D0, D1, D3, DB, S00, S01, S10, S11

S01S10S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D2, D3, DB, S00, S01, S10, S11

S01S10S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D0, DB, D2, D3, S00, S01, S10, S11

Combinational

S01S10S11

FamilyModules

Seq Comb

All listed 1

Input Output

Function

D1, D2, D3, DB, S00, S01, S10, S11

A, S, B, C, D Y

FamilyModules

Seq Comb

All listed 1

Input Output

Carry Select for Implementing High Speed Adders

Truth Table A S B C D Y

X X X 0 0 0

0 X 0 0 X 0

0 X 0 1 X 1

0 0 X 0 X 0

0 0 X 1 X 1

X 1 1 X 1 1

X 1 1 X 0 0

1 X X X 1 1

1 X X X 0 0

X X X 1 1 1

Function

Carry Generator

A, S, B, C, D Y

FamilyModules

Seq Comb

All listed 1

Input Output

Carry Select for Implementing High Speed Adders

Truth Table A S B C D Y

X X X 0 0 0

X X 0 0 X 0

X X 0 1 X 1

0 0 X 0 X 0

0 0 X 1 X 1

X 1 1 X 1 1

X 1 1 X 0 0

1 X 1 X 1 1

1 X 1 X 0 0

X X X 1 1 1

Function

A1, B1, A0, B0 Y

FamilyModules

Seq Comb

All listed 1

Input Output

Carry Generator

Truth Table A1 B1 A0 B0 Y

X 0 X 0 0

X 0 0 X 0

0 0 X X 0

0 X X 0 0

0 X 0 X 0

X 1 1 1 1

1 X 1 1 1

1 1 X X 1

Function

Sequential, D-Type Flip-Flop

A1, B1, A0, B0 Y

FamilyModules

Seq Comb

All listed 1

Input Output

Carry Generator

Truth Table

A1 B1 A0 B0 Y

X 0 0 0 0

0 0 X X 0

0 X 0 0 0

X 1 X 1 1

X 1 1 X 1

1 X X 1 1

1 X 1 X 1

1 1 X X 1

Function

D, CLK Q

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1

Input Output

D-Type Flip-Flop

Truth Table

CLK Qn+1

Function

D, CLK QN

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with active low Output

Truth Table

CLK QNn+1

↑ !D

Function

ACT 1, ACT 2, ACT 3, 3200DX, MX

D, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with active low Clock

Truth Table

CLK Qn+1

Function

D, CLK QN

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with active low Clock and Output

Truth Table

CLK QNn+1

↓ !D

Function

ACT 1, MX,ACT2/1200XL, ACT3, 3200DX, MX

CLR, D, CLK Q

* A 2 on the symbol implies 2 logic module delays on all families except ACT1 and MX.

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1 1

Input Output

D-Type Flip-Flop with active high Clear

Truth Table

CLR CLK Qn+1

0 ↑ D

Function

CLR, D, CLK Q

* A 2 on the symbol implies 2 logic module delays on all families except ACT1 and MX.

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1 1

Input Output

D-Type Flip-Flop with active high Clear and active low Clock

Truth Table

CLR CLK Qn+1

0 ↓ D

Function

CLR, D, CLK Q

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1

Input Output

D-Type Flip-Flop with active low Clear

Truth Table

CLR CLK Qn+1

1 ↑ D

Function

ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SxaACT 1, ACT 2, ACT 3, 3200DX, MX SX, SX-A, SX-S, eX, AxceleratorDFC1B

CLR, D, CLK QN

FamilyModules

Seq Comb

ACT 1; MX 2

Input Output

D-Type Flip-Flop with active high Clear and Clock

Truth Table

CLR CLK QNn+1

0 ↑ !D

Function

ACT 1, MX

CLR, D, CLK Q

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1

Input Output

D-Type Flip-Flop with active low Clear and Clock

Truth Table

CLR CLK Qn+1

1 ↓ D

Function

CLR, D, CLK QN

* A 2 on the symbol implies 2 logic module delays except for ACT1 and MX.

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1 1

Input Output

D-Type Flip-Flop with active low Clear and Output

Truth Table

CLR CLK QNn+1

1 ↑ !D

Function

CLR, D, CLK QN

FamilyModules

Seq Comb

ACT 1, MX 2

Input Output

D-Type Flip-Flop with active high Clear, active low Clock and Output

Truth Table

CLR CLK QNn+1

0 ↓ !D

Function

ACT 1, MX

Sequential D-Type Flip-Flop with Enable

CLR, D, CLK QN

* A 2 on the symbol implies 2 logic module delays except for ACT1 and MX.

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1 1

Input Output

D-Type Flip-Flop with active low Clear, Clock and Output

Truth Table

CLR CLK Qn+1

1 ↓ !D

Function

ACT 1, ACT2/1200XL, ACT 3, 3200DX, MX

D, E, CLK Q

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1

Input Output

D-Type Flip-Flop with active high Enable

Truth Table

E CLK Qn+1

1 ↑ D

Function

D, E, CLK Q

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1

Input Output

D-Type Flip-Flop with active low Enable

Truth Table

E CLK Qn+1

0 ↑ D

Function

ACT 1, ACT2/1200XL, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Axcelerator

D, E, CLK Q

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1

Input Output

D-Type Flip-Flop with active low Enable and Clock

Truth Table

E CLK Qn+1

0 ↓ D

Function

ACT 1, ACT2/1200XL, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX, Axcelerator

CLKCLR

CLR, D, E, PRE, CLK Q

* Your design should not allow both PRE and CLR to be asserted at the same time.

FamilyModules

Seq Comb

ACT 1, MX 2

Input Output

D-Type Flip-Flop with active high Preset, active low Enable, Clear, and Clock

Truth Table

CLR PRE E CLK Qn+1

0 0 X X 0

1 1 X X 1

1 0 1 X Q

1 0 0 ↓ D

0 1 X X *

Function

ACT 1, MX

CLRCLK

CLR, D, E, CLK Q

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1

Input Output

D-Type Flip-Flop, with Enable and active low Clear

Truth Table

CLR E CLK Qn+1

0 X X 0

1 0 X Q

1 1 ↑ D

Function

CLRCLK

CLR, D, E, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with Enable and active low Clear and Clock

Truth Table

CLR E CLK Qn+1

0 X X 0

1 0 X Q

1 1 ↓ D

Function

CLRCLK

CLR, D, E, CLK Q

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1

Input Output

D-Type Flip-Flop with Active Low Enable and Clear

Truth Table

CLR E CLK Qn+1

0 X X 0

1 1 X Q

1 0 ↑ D

Function

CLRCLK

CLR, D, E, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with active low Enable, Clear and Clock

Truth Table

CLR E CLK Qn+1

0 X X 0

1 1 X Q

1 0 ↓ D

Function

D, E, PRE, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with active high Enable and Preset

Truth Table

PRE E CLK Qn+1

1 X X 1

0 0 X Q

0 1 ↑ D

Function

ACT 1, MX

D, E, PRE, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with active high Enable and Preset, and active low Clock

Truth Table

PRE E CLK Qn+1

1 X X 1

0 0 X Q

0 1 ↓ D

Function

ACT 1, MX

D, E, PRE, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with active low Enable, and active high Preset

Truth Table

PRE E CLK Qn+1

1 X X 1

0 1 X Q

0 0 ↑ D

Function

ACT 1, MX

D, E, PRE, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with active low Enable and Clock, and active high Preset

Truth Table

PRE E CLK Qn+1

1 X X 1

0 1 X Q

0 0 ↓ D

Function

ACT 1, MX

D, E, PRE, CLK Q

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with active low Enable and Preset

Truth Table

PRE E CLK Qn+1

0 X X 1

1 1 X Q

1 0 ↑ D

Function

D, E, PRE, CLK Q

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with active low Enable, Clock, and Preset

Truth Table

PRE E CLK Qn+1

0 X X 1

1 1 X Q

1 0 ↓ D

Function

D, E, CLK Q

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1

Input Output

D-Type Flip-Flop, with Enable, and active low Clock

Truth Table

E CLK Qn+1

1 ↓ D

Function

CLRCLK

*Your design should not allow both PRE and CLR to be asserted at the same time.

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with Enable, Preset, and active low Clear

Truth Table

CLR PRE E CLK Qn+1

0 0 X X 0

1 1 X X 1

1 0 0 X Q

1 0 1 ↑ D

0 1 X X *

Function

ACT 1, MX

CLKCLR

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with Enable, Preset, and active low Clear and Clock

Truth Table

CLR PRE E CLK Qn+1

0 0 X X 0

1 1 X X 1

1 0 0 X Q

1 0 1 ↓ D

0 1 X X *

Function

ACT 1, MX

CLKCLR

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with active low Enable and Clear, and active high Preset

Truth Table

CLR PRE E CLK Qn+1

0 0 X X 0

1 1 X X 1

1 0 1 X Q

1 0 0 ↑ D

0 1 X X *

Function

ACT 1, MX

CLKCLR

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with active low Enable, Preset, and Clear

Truth Table

CLR PRE E CLK Qn+1

0 X X X 0

1 0 X X 1

1 1 1 X Q

1 1 0 ↑ D

Function

CLKCLR

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with active low Enable, Clear, Preset, and Clock

Truth Table

CLR PRE E CLK Qn+1

0 X X X 0

1 0 X X 1

1 1 1 X Q

1 1 0 ↓ D

Function

D, E, CLK Q

NOTE 1: The CLK pin must be driven by the IOCLKBUF macro.WARNING: Using the IODFE macro will disable the IOPCLBUF clock network.NOTE 2: Uses an I/O module.

Input Output

Truth Table

E CLK Qn+1

0 ↑ D

Function

IODFEC

IOPCLCLK

IOPCL, D, E, CLK Q

NOTE 1: The CLK pin must be driven by the IOCLKBUF macro.NOTE 2: Uses an I/O module.NOTE 3: The IOPCL pin must be driven by the IOPCLBUF macro.

Input Output

D-Type Flip-Flop with active low Enable and Clear

Truth Table

IOPCL E CLK Qn+1

0 X X 0

1 1 X Q

1 0 ↑ D

Function

IODFEP

IOPCLQ

IOPCL, D, E, CLK Q

NOTE 1: The CLK pin must be driven by the IOCLKBUF macro.NOTE 2: The IOPCL pin must be driven by the IOPCLBUF macro.NOTE 3: Uses an I/O module.

Input Output

D-Type Flip-Flop with active low Enable and Preset

Truth Table

IOPCL E CLK Qn+1

0 X X 1

1 1 X Q

1 0 ↑ D

Function

Sequential, D-Type Flip-Flop with Multiplexed Data

A, B, S, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data

Truth Table

S CLK Qn+1

0 ↑ A

1 ↑ B

Function

ACT 1, ACT2/1200XL, ACT 3, 3200DX, MX, Axcelerator

CLK, A, B, S, E, PRE, CLR Q

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, rising-edge triggered Clock, and active-low Enable, Preset, and Clear

Truth Table

CLR PRE E S CLK Qn+1

0 X X X X 0

1 0 X X X 1

1 1 1 X X Q

1 1 0 0 ↑ A

1 1 0 1 ↑ B

Function

Axcelerator

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, falling-edge triggered Clock, and active-low Enable, Preset, and Clear

Truth Table

CLR PRE E S CLK Qn+1

0 X X X X 0

1 0 X X X 1

1 1 1 X X Q

1 1 0 0 ↓ A

1 1 0 1 ↓ B

Function

Axcelerator

A, B, S, CLK QN

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active low Output

Truth Table

S CLK QNn+1

0 ↑ !A

1 ↑ !B

Function

A, B, S, CLK QN

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active low Clock and Output

Truth Table

S CLK QNn+1

0 ↓ !A

1 ↓ !B

Function

A, B, CLR, S, CLK Q

* A 2 on the symbol implies 2 logic module delays except for ACT 1 and MX.

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active high Clear

Truth Table

CLR S CLK Qn+1

1 x x 0

0 1 ↑ B

0 0 ↑ A

Function

A, B, CLR, S, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active low Clear and Clock

Truth Table

CLR S CLK Qn+1

0 X X 0

1 0 ↓ A

1 1 ↓ B

Function

ACT 1, ACT2/1200XL, ACT 3, 3200DX, MX, Axcelerator

A, B, CLR, S, CLK Q

* A 2 on the symbol implies 2 logic module delays except for ACT 1 and MX.

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, Clear, and active low Clock

Truth Table

CLR S CLK Qn+1

1 X X 0

0 0 ↓ A

0 1 ↓ B

Function

A, B, CLR, S, CLK QN

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, Clear, and active low Output

Truth Table

CLR S CLK QNn+1

1 X X 1

0 0 ↑ !A

0 1 ↑ !B

Function

ACT 1, MX

A, B, CLR, S, CLK QN

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, Clear, and active low Clock and Output

Truth Table

CLR S CLK QNn+1

1 X X 1

0 0 ↓ !A

0 1 ↓ !B

Function

ACT 1, MX

A, B, PRE, S, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active high Preset

Truth Table

PRE S CLK Qn+1

1 X X 1

0 0 ↑ A

0 1 ↑ B

Function

ACT 1, MX

A, B, PRE, S, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active low Preset

Truth Table

PRE S CLK Qn+1

0 X X 1

1 0 ↑ A

1 1 ↑ B

Function

ACT 1, MX, Axcelerator

A, B, PRE, S, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active low Preset and Clock

Truth Table

PRE S CLK Qn+1

0 X X 1

1 0 ↓ A

1 1 ↓ B

Function

ACT 1, MX, Axcelerator

A, B, PRE, S, CLK QN

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active low Preset and Output

Truth Table

PRE S CLK QNn+1

0 X X 0

1 0 ↑ !A

1 1 ↑ !B

Function

A, B, PRE, S, CLK QN

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active low Preset, Clock and Output

Truth Table

PRE S CLK QNn+1

0 X X 0

1 0 ↓ !A

1 1 ↓ !B

Function

A, B, PRE, S, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, Preset, and active low Clock

Truth Table

PRE S CLK Qn+1

1 X X 1

0 0 ↓ A

0 1 ↓ B

Function

ACT 1, MX

A, B, CLR, PRE, S, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, Preset, and active low Clear

Truth Table

CLR PRE S CLK Qn+1

0 0 X X 0

1 1 X X 1

1 0 0 ↑ A

1 0 1 ↑ B

0 1 X X *

Function

ACT 1, MX

A, B, CLR, PRE, S, CLK Q

FamilyModules

Seq Comb

All listed 2

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, Preset, and active low Clear and Clock

Truth Table

CLR PRE S CLK Qn+1

0 0 X X 0

1 1 X X 1

1 0 0 ↓ A

1 0 1 ↓ B

0 1 X X *

Function

ACT 1, MX

CLKS1S0

D3D2D1D0

D0, D1, D2, D3, S0, S1, Q CLK, CLR

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with 4-input Multiplexed Data, active low Clear, and active high Clock

Truth Table

CLR S1 S0 CLK Qn+1

0 X X X 0

1 0 0 ↑ D0

1 0 1 ↑ D1

1 1 0 ↑ D2

1 1 1 ↑ D3

Function

ACT 2, ACT 3, 3200DX, MX

CLKS1S0

D3D2D1D0

D0, D,1 D2, D3 S0, S1, QCLK, CLR

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with 4-input Multiplexed Data, active low Clear, and Clock

Truth Table

CLR S1 S0 CLK Qn+1

0 X X X 0

1 0 0 ↓ D0

1 0 1 ↓ D1

1 1 0 ↓ D2

1 1 1 ↓ D3

Function

D0D1D2D3

S10S11S0CLK

D0, D1, D2, D3, S0, S10, QS11, CLK, CLR

NOTE 1: The DFM7A macro represents the full ACT 2, 3200DX and MX S-module.

NOTE 2: The following schematic describes the interconnections of the select lines.

FamilyModules

Seq Comb

All listed 1

S10S11

Input Output

Truth Table

CLR S11 S10 S0 CLK Qn+1

0 X X X X 0

1 0 0 0 ↑ D0

1 0 0 1 ↑ D1

1 1 X 0 ↑ D2

1 X 1 0 ↑ D2

1 1 X 1 ↑ D3

1 X 1 1 ↑ D3

Function

D0D1D2D3

S10S11S0

D0, D1, D2, D3, S0, S10, QS11, CLK, CLR

NOTE 1: The DFM7B macro represents the full ACT 2, 3200DX and MX S-module.NOTE 2: The following schematic describes the interconnections of the select lines.

FamilyModules

Seq Comb

All listed 1

S10S11

Input Output

D-Type Flip-Flop with 4-input Multiplexed Data, active low Clear and Clock

Truth Table

CLR S11 S10 S0 CLK Qn+1

0 X X X X 0

1 0 0 0 ↓ D0

1 0 0 1 ↓ D1

1 1 X 0 ↓ D2

1 X 1 0 ↓ D2

1 1 X 1 ↓ D3

1 X 1 1 ↓ D3

Function

QD0D1D2D3

S10S11

D0, D1, D2, D3, S00, QS01, S10, S11, CLK, CLR

NOTE 1: The DFM8A macro represents the full ACT 3 S-Module.NOTE 2: The following schematic describes the interconnections of the select lines.

FamilyModules

Seq Comb

ACT3 1

S0S1D3

S01S00

S10S11

Input Output

Truth Table

CLR S11 S10 S01 S00 CLK Qn+1

0 X X X X X 0

1 0 0 0 X ↑ D0

1 0 0 X 0 ↑ D0

1 0 0 1 1 ↑ D1

1 1 X 0 X ↑ D2

1 X 1 0 X ↑ D2

1 1 X X 0 ↑ D2

1 X 1 X 0 ↑ D2

1 1 X 1 1 ↑ D3

1 X 1 1 1 ↑ D3

Function

S11S10

D3D2D1D0 Q

D0, D1, D2, D3, S00, S01, QS10, S11, CLK, CLR

NOTE 1: The DFM8B macro represents the full ACT 3 S-Module.NOTE 2: The following schematic describes the interconnections of the select lines.

FamilyModules

Seq Comb

ACT3 1

S0S1D3

S01S00

S10S11

Input Output

D-Type Flip-Flop with 4-input Multiplexed Data, active low Clear and Clock

Truth Table

CLR S11 S10 S01 S00 CLK Qn+1

0 X X X X X 0

1 0 0 0 X ↓ D0

1 0 0 X 0 ↓ D0

1 0 0 1 1 ↓ D1

1 1 X 0 X ↓ D2

1 X 1 0 X ↓ D2

1 1 X X 0 ↓ D2

1 X 1 X 0 ↓ D2

1 1 X 1 1 ↓ D3

1 X 1 1 1 ↓ D3

Function

A, B, S, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active low Clock

Truth Table

S CLK Qn+1

0 ↓ A

1 ↓ B

Function

ACT 1, ACT 2, ACT 3, 3200DX, MX, Axcelerator

A, B, CLR, S, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active low Clear

Truth Table

CLR S CLK Qn+1

0 X X 0

1 0 ↑ A

1 1 ↑ B

Function

Sequential, D-Type Flip-Flop with Preset

DFME1A

A, B, S, E, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

2-bit D-Type Flip-Flop with Multiplexed Data, and active low Enable

Truth Table

E S CLK Qn+1

1 X X Q

0 0 ↑ A

0 1 ↑ B

Function

DFME1B

CLK, A, B, S, E, Q

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, falling-edge triggered Clock, and active-low Enable

Truth Table

E S CLK Qn+1

1 X X Q

0 0 ↓ A

0 1 ↓ B

Function

Axcelerator

DFME2A

CLK, A, B, S, E, PRE Q

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, rising-edge triggered Clock, and active-low Enable and Preset

Truth Table

PRE E S CLK Qn+1

0 X X X 1

1 1 X X Q

1 0 0 ↑ A

1 0 1 ↑ B

Function

Axcelerator

DFME2B

CLK, A, B, S, E, PRE Q

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, falling-edge triggered Clock, and active-low Enable and Preset

Truth Table

PRE E S CLK Qn+1

0 X X X 1

1 1 X X Q

1 0 0 ↓ A

1 0 1 ↓ B

Function

Axcelerator

DFME3A

CLKCLR

CLK, A, B, S, E, CLR Q

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, rising-edge triggered Clock, and active-low Enable and Clear

Truth Table

CLR E S CLK Qn+1

0 X X X 0

1 1 X X Q

1 0 0 ↑ A

1 0 1 ↑ B

Function

Axcelerator

DFME3B

CLKCLR

CLK, A, B, S, E, CLR Q

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, falling-edge triggered Clock, and active-low Enable and Clear

Truth Table

CLR E S CLK Qn+1

0 X X X 0

1 1 X X Q

1 0 0 ↓ A

1 0 1 ↓ B

Function

Axcelerator

DFMPCA

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, rising-edge triggered Clock, and active-low Preset and Clear

Truth Table

CLR PRE S CLK Qn+1

0 X X X 0

1 0 X X 1

1 1 0 ↑ A

1 1 1 ↑ B

Function

Axcelerator

DFMPCB

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, falling-edge triggered Clock, and active-low Preset and Clear

Truth Table

CLR PRE S CLK Qn+1

0 X X X 0

1 0 X X 1

1 1 0 ↓ A

1 1 1 ↓ B

Function

Axcelerator

D, PRE, CLK Q

* A 2 on the symbol implies 2 logic module delays only for SX, SX-A, SX-S, eX, and Axcelerator.

FamilyModules

Seq Comb

SX, SX-A, SX-S, eX, Axcelerator 1 1

Others 2

Input Output

D-Type Flip-Flop with active high Preset

Truth Table

PRE CLK Qn+1

0 ↑ D

Function

D, PRE, CLK Q

* A 2 on the symbol implies 2 logic module delays only for SX, SX-A, SX-S, eX, and Axcelerator.

FamilyModules

Seq Comb

SX, SX-A, eX, Axcelerator 1 1

Others 2

Input Output

D-Type Flip-Flop with active high Preset, and active low Clock

Truth Table

PRE CLK Qn+1

0 ↓ D

Function

D, PRE, CLK Q

FamilyModules

Seq Comb

SX, SX-A, SX-S, eX, Axcelerator 1

Others 2

Input Output

D-Type Flip-Flop with active low Preset

Truth Table

PRE CLK Qn+1

1 ↑ D

Function

D, PRE, CLK QN

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1 1

Input Output

D-Type Flip-Flop with active high Preset, and active low Output

Truth Table

PRE CLK QNn+1

0 ↑ !D

Function

D, PRE, CLK Q

FamilyModules

Seq Comb

SX, SX-A, SX-S, eX, and Axcelerator 1

Others 2

Input Output

D-Type Flip-Flop with active low Preset and Clock

Truth Table

PRE CLK Qn+1

1 ↓ D

Function

D, PRE, CLK QN

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with active low Preset and Output

Truth Table

PRE CLK QNn+1

1 ↑ !D

Function

D, PRE, CLK QN

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1 1

Input Output

D-Type Flip-Flop with active high Preset, and active low Clock and Output

Truth Table

PRE CLK QNn+1

0 ↓ !D

Function

D, PRE, CLK QN

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

D-Type Flip-Flop with active low Preset, Clock and Output

Truth Table

PRE CLK QNn+1

1 ↓ !D

Function

Sequential, D-Type Flip-Flop with Preset and Clea r

CLRCLK

CLR, D, PRE, CLK Q

* A 2 on the symbol implies 2 logic module delays only for SX, SX-A, SX-S, and eX.** In ACT 1/MX, your design should not allow both PRE and CLR to be asserted at the same time. In other families, CLR has priority over PRE.

FamilyModules

Seq Comb

Others 1 1

ACT 1, ACT2/1200XL, ACT 3, 3200DX, MX, SX, SX-A, SX-S 2

Input Output

D-Type Flip-Flop with active high Preset, active low Clear, and active high Clock

Truth Table

CLR PRE CLK Qn+1

0 0 X 0

1 1 X 1

1 0 ↑ D

0 1 X **

Function

CLRCLK

CLR, D, PRE, CLK Q

FamilyModules

Seq Comb

Input Output

D-Type Flip-Flop with active high Preset, active low Clear and Clock

Truth Table

CLR PRE CLK Qn+1

0 0 X 0

1 1 X 1

1 0 ↓ D

0 1 X *

Function

Sequential, Data Latc

CLKCLR

CLR, D, PRE, CLK Q

FamilyModules

Seq Comb

SX, SX-A, SX-S, eX, Axcelerator 1

Input Output

D-Type Flip-Flop, with active low Clear, and Preset

Truth Table

CLR PRE CLK Qn+1

0 X X 0

1 0 X 1

1 1 ↑ D

Function

CLKCLR

CLR, D, PRE, CLK Q

FamilyModules

Seq Comb

All listed 1

Input Output

D-Type Flip-Flop with active low Preset, Clear and Clock

Truth Table

CLR PRE CLK Qn+1

0 X X 0

1 0 X 1

1 1 ↓ D

Function

D, G Q

FamilyModules

Seq Comb

ACT 1, MX, SX, SX-A, SX-S, eX 1

Others 1

Input Output

Data Latch

Truth Table

G Qn+1

Function

ACT 1, ACT 2, ACT3, 3200DX, MX, SX, SX-A, SX-S, eX, Axcelerator

D, G QN

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

Data Latch with active low Output

Truth Table

G QNn+1

Function

ACT 1, ACT 2, ACT3, 3200DX, MX, Axcelerator

D, G Q

FamilyModules

Seq Comb

Others 1

Input Output

Data Latch with active low Clock

Truth Table

G Qn+1

Function

D, G QN

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

Data Latch, with active low Clock and Output

Truth Table

G QNn+1

Function

CLR, D, G, PRE Q

*In ACT 1 and MX, your design should not allow PRE and CLR to be asserted at the same time. In other families, CLR has priority over PRE.

FamilyModules

Seq Comb

ACT 1/MX 1

Others 2

Input Output

Data Latch with active low Clear and active high Preset

Truth Table

CLR PRE G Qn+1

0 0 X 0

1 1 X 1

1 0 0 Q

1 0 1 D

0 1 X *

Function

PRE QN

CLR, D, G, PRE QN

FamilyModules

Seq Comb

ACT 1/MX 1

Others 2

Input Output

Data Latch with active high Clear and active low Preset, Clock, and Output

Truth Table

CLR PRE G QNn+1

1 1 X 1

0 0 X 0

0 1 1 QN

0 1 0 !D

1 0 X *

Function

ACT 1, ACT 2, ACT3, 3200DX, MX

CLR, D, G, PRE Q

FamilyModules

Seq Comb

ACT 1/MX 1

Others 2

Input Output

Data Latch with active low Clear, active high Preset, and active low Clock

Truth Table

CLR PRE G Qn+1

0 0 X 0

1 1 X 1

1 0 1 Q

1 0 0 D

0 1 X *

Function

Sequential, Data Latch with Clear

CLR, D, G, PRE QN

FamilyModules

Seq Comb

ACT 1/MX 1

Others 2

Input Output

Data Latch with active high Clear and active low Preset and Output

Truth Table

CLR PRE G QNn+1

1 1 X 1

0 0 X 0

0 1 0 QN

0 1 1 !D

1 0 X *

Function

ACT 1, ACT 2, ACT3, 3200DX, MX

CLR, D, G Q

FamilyModules

Seq Comb

Others 1

Input Output

Data Latch with active low Clear

Truth Table

CLR G Qn+1

Function

CLR, D, G Q

FamilyModules

Seq Comb

Input Output

Data Latch with active high Clear

Truth Table

CLR G Qn+1

Function

CLR, D, G Q

FamilyModules

Seq Comb

Input Output

Data Latch with active high Clear and active low Clock

Truth Table

CLR G Qn+1

Function

CLR, D, G QN

FamilyModules

Seq Comb

ACT 1/MX 1

Others 2

Input Output

Data Latch with active high Clear and active low Output

Truth Table

CLR G QNn+1

0 0 QN

0 1 !D

Function

CLR, D, G QN

FamilyModules

Seq Comb

ACT 1/MX 1

Others 2

Input Output

Data Latch with active high Clear and active low Clock and Output

Truth Table

CLR G QNn+1

0 1 QN

0 0 !D

Function

Sequential, Data Latch with Enable and Clear

CLR, D, G Q

FamilyModules

Seq Comb

Others 1

ACT 2, 1200XL, ACT 3, 3200DX, MX 1

Input Output

Data Latch with active low Clear and Clock

Truth Table

CLR G Qn+1

Function

D, E, G Q

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

Data Latch with active high Enable

Truth Table

E G Qn+1

Function

D, E, G QN

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

Data Latch with active low Enable and Clock and active low Output

Truth Table

E G QNn+1

1 X QN

X 1 QN

0 0 !D

Function

CLR, D, E, G Q

FamilyModules

Seq Comb

ACT 1/MX 1

Input Output

Data Latch with active high Enable and Clear, and active low Clock

Truth Table

CLR E G Qn+1

1 X X 0

0 0 X Q

0 X 1 Q

0 1 0 D

Function

ACT 1, MX

CLR, D, E, G Q

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

Data Latch with active low Enable, Clear, and Clock

Truth Table

CLR E G Qn+1

0 X X 0

1 1 X Q

1 X 1 Q

1 0 0 D

Function

CLR, D, E, G Q

FamilyModules

Seq Comb

Input Output

Data Latch with active low Enable and Clock, and active high Clear

Truth Table

CLR E G Qn+1

1 X X 0

0 1 X Q

0 X 1 Q

0 0 0 D

Function

Sequential, Data Latch with Enable and Preset

D, E, G, PRE Q

FamilyModules

Seq Comb

ACT 1/MX 1

Input Output

Data Latch with active high Enable and Preset, and active low Clock

Truth Table

PRE E G Qn+1

1 X X 1

0 0 X Q

0 1 0 D

0 X 1 Q

Function

ACT 1, MX

D, E, G, PRE Q

FamilyModules

Seq Comb

Input Output

Data Latch with active low Enable and Clock, and active high Preset

Truth Table

PRE E G Qn+1

1 X X 1

0 1 X Q

0 X 1 Q

0 0 0 D

Function

D, E, G, PRE Q

FamilyModules

Seq Comb

Input Output

Data Latch with active low Enable, Preset, and Clock

Truth Table

PRE E G Qn+1

0 X X 1

1 1 X Q

1 X 1 Q

1 0 0 D

Function

D, E, G Q

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

Data Latch with active low Enable and active high Clock

Truth Table

E G Qn+1

Function

Data Latch

D, E, G Q

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

Data Latch with active high Enable, and active low Clock

Truth Table

E G Qn+1

Function

D, E, G Q

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

Data Latch with active low Enable and Clock

Truth Table

E G Qn+1

Function

Sequential

A, B, S, G Q

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

Data Latch with 2-input Multiplexed Data

Truth Table

S G Qn+1

Function

A, B, S, G, CLR Q

FamilyModules

Seq Comb

All listed 1

Input Output

Data Latch with 2-input Multiplexed Data and Active-Low Clear

Truth Table

CLR S G Qn+1

0 X X 0

1 X 0 Q

1 0 1 A

1 1 1 B

Function

ACT 2, ACT 3, 3200DX, MX, Axcelerator

Data Latch with Multiplexed Data

A, B, CLR, S, G Q

FamilyModules

Seq Comb

ACT 1/MX 1

Input Output

Data Latch with 2-input Multiplexed Data and Clear, and Active-Low Clock

Truth Table

CLR S G Qn+1

1 X X 0

0 X 1 Q

0 0 0 A

0 1 0 B

Function

ACT 1, MX

A, B, CLR, S, G Q

FamilyModules

Seq Comb

All listed 1

Input Output

Data Latch with 2-input Multiplexed Data and Active-Low Clock and Clear

Truth Table

CLR S G Qn+1

0 X X 0

1 X 1 Q

1 0 0 A

1 1 0 B

Function

D3D2D1D0

D0, D1, D2, D3, S0, S1, Q G

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table S1 S0 G Qn+1

X X 0 Q

0 0 1 D0

0 1 1 D1

1 0 1 D2

1 1 1 D3

Function

D3D2D1D0

D0, D1, D2, D3, S0, S1, Q G

FamilyModules

Seq Comb

All listed 1

Input Output

Data Latch with 4-input Multiplexed Data, and active low Clock

Truth Table

S1 S0 G Qn+1

X X 1 Q

0 0 0 D0

0 1 0 D1

1 0 0 D2

1 1 0 D3

Function

D0D1D2D3

S0S10S11G

D0, D1, D2, D3, S0, S10, Q S11, G

FamilyModules

Seq Comb

All listed 1

Input Output

Truth Table

S10 S11 S0 G Qn+1

X X X 0 Q

0 0 0 1 D0

0 0 1 1 D1

X 1 0 1 D2

1 X 0 1 D2

X 1 1 1 D3

1 X 1 1 D3

Function

D0D1D2D3

S0S10S11G

D0, D1, D2, D3, S0, S10, Q S11, G

FamilyModules

Seq Comb

All listed 1

Input Output

Data Latch with 4-input Multiplexed Data and active low Clock

Truth Table

S10 S11 S0 G Qn+1

X X X 1 Q

0 0 0 0 D0

0 0 1 0 D1

X 1 0 0 D2

1 X 0 0 D2

X 1 1 0 D3

1 X 1 0 D3

Function

QD0D1D2D3

S10S11

D0, D1, D2, D3, S00, Q S01, S10, S11, G, CLR

NOTE 1: The DLM8A macro represents the full ACT 3 S-Module.

FamilyModules

Seq Comb

ACT 3 1

S0S1D3

S01S00

S10S11

Input Output

D-Type Latch with 4-input Multiplexed Data and active low Clear

Truth Table CLR S11 S10 S01 S00 G Qn+1

0 X X X X X 0

1 X X X X 0 Q

1 0 0 0 X 1 D0

1 0 0 X 0 1 D0

1 0 0 1 1 1 D1

1 1 X 0 X 1 D2

1 X 1 0 X 1 D2

1 1 X X 0 1 D2

1 X 1 X 0 1 D2

1 1 X 1 1 1 D3

1 X 1 1 1 1 D3

Function

S11S10

D3D2D1D0 Q

D0, D1, D2, D3, S00, QS01, S10, S11, G, CLR

NOTE 1: The DLM8B macro represents the full ACT 3 S-Module.

FamilyModules

Seq Comb

ACT 3 1

S0S1D3

S10S11

S01S00

Input Output

D-Type Latch with 4-input Multiplexed Data and active low Clear and Clock

Truth Table CLR S11 S10 S01 S00 G Qn+1

0 X X X X X 0

1 X X X X 1 Q

1 0 0 0 X 0 D0

1 0 0 X 0 0 D0

1 0 0 1 1 0 D1

1 1 X 0 X 0 D2

1 X 1 0 X 0 D2

1 1 X X 0 0 D2

1 X 1 X 0 0 D2

1 1 X 1 1 0 D3

1 X 1 1 1 0 D3

Function

A, B, G, S Q

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

Data Latch with 2-input Multiplexed Data and active low Clock

Truth Table

S G Qn+1

Function

DLME1A

A, B, E, G, S Q

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

2-bit Data Latch with Multiplexed Data and Enable and active low Clock and Enable

Truth Table

E S G Qn+1

1 X X Q

X X 1 Q

0 0 0 A

0 1 0 B

Function

Sequential, Data Latch with Preset

D, G, PRE Q

FamilyModules

Seq Comb

Input Output

Data Latch with active high Preset and Clock

Truth Table

PRE G Qn+1

Function

D, G, PRE Q

FamilyModules

Seq Comb

Input Output

Data Latch with active high Preset and active low Clock

Truth Table

PRE G Qn+1

Function

D, G, PRE Q

FamilyModules

Seq Comb

Input Output

Data Latch with active low Preset and active high Clock

Truth Table

PRE G Qn+1

Function

D, G, PRE Q

FamilyModules

Seq Comb

Input Output

Data Latch with active low Preset and Clock

Truth Table

PRE G Qn+1

Function

Sequential, JK Flip-Flop

PRE QN

D, G, PRE QN

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

Data Latch with active low Preset and Output, and active high Clock

Truth Table

PRE G QNn+1

1 0 QN

1 1 !D

Function

D, G, PRE QN

FamilyModules

Seq Comb

ACT 1/MX 1

Others 1

Input Output

Data Latch with active low Preset, Clock, and Output

Truth Table

PRE G Qn+1

1 0 !D

1 1 QN

Function

Combinational, Wide Decode

DXAND7

A, B, C, D, E, F, G Y

FamilyModules

Seq DX

3200DX/ MX 1

Input Output

Seven-input AND Gate

Truth Table

A through G Y

All inputs = 1 1

Any input = 0 0

Function

3200DX, MX

A, B, C, D, E, F, G, H Y

FamilyModules

Seq DX

3200DX/ MX 1

Input Output

Eight-input AND/Exclusive-OR Gate

Truth Table

A through G H Y

Any input = 0 0 0

Any input = 0 1 1

All inputs = 1 0 1

All inputs = 1 1 0

Function

3200DX, MX

DXNAND7

A, B, C, D, E, F, G Y

FamilyModules

Seq DX

3200DX/ MX 1

Input Output

Seven-input NAND Gate

Truth Table

A through G Y

All inputs = 1 0

Any input = 0 1

Function

3200DX, MX

A, B, CI CO, S

* A 2 on the symbol implies 2 logic module delays only in ACT 1 and MX.

FamilyModules

Seq Comb

ACT 1/ MX 3

Input Output

1 bit adder with active high I/Os

Truth Table A B CI S CO

0 0 0 0 0

1 0 0 1 0

0 1 0 1 0

1 1 0 0 1

0 0 1 1 0

1 0 1 0 1

0 1 1 0 1

1 1 1 1 1

Function

ACT 1, MX, SX, SX-A, SX-S, eX, Axcelerator

A, B, CI CO, S

* A 2 on the symbol implies 2 logic module delays in all families except SX and SXA.

FamilyModules

Seq Comb

Input Output

1-bit Adder, with active low Carry In and Carry Out, and active low A-Input

Truth Table A B CI S CO

0 0 0 0 0

0 0 1 1 1

0 1 0 1 0

0 1 1 0 0

1 0 0 1 1

1 0 1 0 1

1 1 0 0 0

Function

A, B, CI CO, S

* A 2 on the symbol implies 2 logic module delays in all families except SX and SXA.

FamilyModules

Seq Comb

Input Output

1-bit Adder with active low Carry In and Carry Out

Truth Table A B CI CO S

0 0 0 1 1

0 0 1 1 0

0 1 0 0 0

0 1 1 1 1

1 0 0 0 0

1 0 1 1 1

1 1 0 0 1

Function

A0, A1, B, CI CO, S

* A 2 on the symbol implies 2 logic module delays in all families.

FamilyModules

Seq Comb

Input Output

1-bit Adder, with active low Carry In and Carry Out, and active low A0 and A1 Inputs, used in multipliers

Truth Table 1

A0 A1 B CI CO S

0 0 0 0 0 0

0 0 0 1 1 1

0 0 1 0 0 1

0 0 1 1 0 0

0 1 0 0 1 1

0 1 0 1 1 0

0 1 1 0 0 0

0 1 1 1 1 1

1 0 0 0 1 1

1 0 0 1 1 0

1 0 1 0 0 0

1 0 1 1 1 1

1 1 0 0 1 1

Function

Combinational, Clock Net Interface

A, G Y

NOTE: G pin can be connected directly to a routed clock (RCLK) or hardwired clock (HCLK) if supported by your device. See your device datasheet for more info.

FamilyModules

Seq Comb

Input Output

2-Input AND Clock Net

Truth TableA G Y

Function

D0, D1, D2, D3, S0, G Y

FamilyModules

Seq Comb

Input Output

4-to-1 Mux Clock Net

Truth TableG S0 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3

Function

GNAND2

A, G Y

FamilyModules

Seq Comb

Input Output

2-Input NAND Clock Net

Truth Table A G Y

Function

NOTE: Ground does not use any modules.

Input Output

GroundFunction

A, G Y

FamilyModules

Seq Comb

Input Output

2-Input NOR Clock Net

Truth Table A G Y

Function

A, G Y

NOTE: G pin can be connected directly to a routed clock (RCLK) if supported by your device. See your device datasheet for more information.

FamilyModules

Seq Comb

Input Output

2-Input OR Clock Net

Truth Table A G Y

Function

Combinational, Half Adder

A, G Y

NOTE: G pin can be connected directly to a routed clock (RCLK) if supported by your device. See your device datasheet for more information.

FamilyModules

Seq Comb

Input Output

2-Input XOR Clock Net

Truth Table A G Y

Function

A, B CO, S

FamilyModules

Seq Comb

Input Output

Half Adder

Truth Table A B CO S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Function

A, B CO, S

FamilyModules

Seq Comb

Input Output

Half-Adder with active low A-Input

0 0 0 1

0 1 1 0

1 0 0 0

1 1 0 1

Function

A, B CO, S

FamilyModules

Seq Comb

Input Output

Half-Adder with active low Carry Out and Sum

0 0 1 1

0 1 1 0

1 0 1 0

1 1 0 1

Function

Combinational, Inverters

A, B CO, S

FamilyModules

Seq Comb

Input Output

Half-Adder with active low Carry Out

0 0 1 0

0 1 1 1

1 0 1 1

1 1 0 0

Function

FamilyModules

Seq Comb

Input Output

Inverter with active low Output

Truth Table A Y

Function

FamilyModules

Seq Comb

Input Output

Inverter with active low OutputNOTE: The Combiner will not remove this macro

Truth Table A Y

Function

FamilyModules

Seq Comb

Input Output

Inverter with active low Input

Truth Table A Y

Function

J, K, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

SX, SX-A, SX-S, eX 1 1

Others 1

Input Output

JK Flip-Flop with active low K-Input

Truth Table J K CLK Qn+1

0 0 ↑ 0

0 1 ↑ Q

1 0 ↑ !Q

1 1 ↑ 1

Function

JK Flip-Flop

J, K, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

JK Flip-Flop with active low Clock and K-Input

Truth Table

J K CLK Qn+1

0 0 ↓ 0

0 1 ↓ Q

1 0 ↓ !Q

1 1 ↓ 1

Function

CLR, J, K, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

JK Flip-Flop with active low Clear and K-Input

Truth Table

CLR J K CLK Qn+1

0 X X X 0

1 0 0 ↑ 0

1 0 1 ↑ Q

1 1 0 ↑ !Q

1 1 1 ↑ 1

Function

CLR, J, K, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

JK Flip-Flop with active low Clear, Clock, and K-Input

Truth Table

CLR J K CLK Qn+1

0 X X X 0

1 0 0 ↓ 0

1 0 1 ↓ Q

1 1 0 ↓ !Q

1 1 1 ↓ 1

Function

CLR, J, K, CLK Q

* A 2 on the symbol implies a 2 logic module delay on all families except ACT1 and MX.

FamilyModules

Seq Comb

ACT 1, MX 2

Others 1 1

Input Output

JK Flip-Flop with active high Clear and active low K-Input

Truth Table

CLR J K CLK Qn+1

1 X X X 0

0 0 0 ↑ 0

0 0 1 ↑ Q

0 1 0 ↑ !Q

0 1 1 ↑ 1

Function

CLR* 2

CLR, J, K, CLK Q

* A 2 on the symbol implies a 2 logic module delay on all families except ACT1 and MX.

FamilyModules

Seq Comb

ACT 1/ MX 2

Others 1 1

Input Output

JK Flip-Flop with active high Clear and active low Clock and K-Input

Truth Table

CLR J K CLK Qn+1

1 X X X 0

0 0 0 ↓ 0

0 0 1 ↓ Q

0 1 0 ↓ !Q

0 1 1 ↓ 1

Function

J, K, PRE, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

JK Flip-Flop with active low Preset and K-Input

Truth Table

PRE J K CLK Qn+1

0 X X X 1

1 0 0 ↑ 0

1 0 1 ↑ Q

1 1 0 ↑ !Q

1 1 1 ↑ 1

Function

J, K, PRE, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

JK Flip-Flop with active low Preset, Clock, and K-Input

Truth Table

PRE J K CLK Qn+1

0 X X X 1

1 0 0 ↓ 0

1 0 1 ↓ Q

1 1 0 ↓ !Q

1 1 1 ↓ 1

Function

J, K, PRE, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

JK Flip-Flop with active high Preset and active low K-Input

Truth Table

PRE J K CLK Qn+1

1 X X X 1

0 0 0 ↑ 0

0 0 1 ↑ Q

0 1 0 ↑ !Q

0 1 1 ↑ 1

Function

ACT 1, MX

Combinational, AND-OR

J, K, PRE, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

JK Flip-Flop with active high Preset, and active low Clock and K-Inputs

Truth Table PRE J K CLK Qn+1

1 X X X 1

0 0 0 ↓ 0

0 0 1 ↓ Q

0 1 0 ↓ !Q

0 1 1 ↓ 1

Function

ACT 1, MX

CLR, J, K, PRE, CLK Q

Your design should not allow both PRE and CLR to be asserted at the same time.

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

JK Flip-Flop with active high Preset, active low Clear, Clock and K-Input

Truth Table

CLR PRE J K CLK Qn+1

0 0 X X X 0

1 1 X X X 1

1 0 0 0 ↓ 0

1 0 0 1 ↓ Q

1 0 1 0 ↓ !Q

1 0 1 1 ↓ 1

0 1 X X X *

Function

ACT 1, MX

CLR, J, K, PRE, CLK Q

FamilyModules

Seq Comb

ACT 1/MX 2

Input Output

JK Flip-Flop with active high Preset, and active low Clear and K- Input

Truth Table

CLR PRE J K CLK Qn+1

0 0 X X X 0

1 1 X X X 1

1 0 0 0 ↑ 0

1 0 0 1 ↑ Q

1 0 1 0 ↑ !Q

1 0 1 1 ↑ 1

0 1 X X X *

Function

ACT 1, MX

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input majority function

Truth Table A B C Y

X 0 0 0

0 0 X 0

0 X 0 0

X 1 1 1

1 X 1 1

1 1 X 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

2 of 3 function

Truth Table A B C Y

0 0 0 0

1 0 0 0

0 1 0 0

1 1 0 1

0 0 1 0

1 0 1 1

0 1 1 1

1 1 1 0

Function

MAJ3XI

A, B, C Y

FamilyModules

Seq Comb

Input Output

2 of 3 function with active low output

Truth Table A B C Y

0 0 0 1

1 0 0 1

0 1 0 1

1 1 0 0

0 0 1 1

1 0 1 0

0 1 1 0

1 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input minority function

Truth Table A B C Y

X 0 0 1

0 0 X 1

0 X 0 1

X 1 1 0

1 X 1 0

1 1 X 0

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

1 of 3 function

Truth Table A B C Y

0 0 0 0

1 0 0 1

0 1 0 1

1 1 0 0

0 0 1 1

1 0 1 0

0 1 1 0

1 1 1 0

Function

MIN3XI

A, B, C Y

FamilyModules

Seq Comb

Input Output

1 of 3 function with active low output

Truth Table A B C Y

0 0 0 1

1 0 0 0

0 1 0 0

1 1 0 1

0 0 1 0

1 0 1 1

0 1 1 1

1 1 1 1

Function

Combinational, Multiplexer

A, B, S Y

FamilyModules

Seq Comb

Input Output

2 to 1 Multiplexer

Truth Table S Y

Function

A, B, S Y

FamilyModules

Seq Comb

Input Output

2 to 1 Multiplexer with active low A-Input

Truth Table S Y

Function

A, B, S Y

FamilyModules

Seq Comb

Input Output

2 to 1 Multiplexer with active low B-Input

Truth Table

Function

A, B, S Y

FamilyModules

Seq Comb

Input Output

2 to 1 Multiplexer with active low Output

Truth Table

Function

D0, S0, S1, D1, D2, D3 Y

FamilyModules

Seq Comb

Input Output

4 to 1 Multiplexer

Truth Table

S1 S0 Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3

Function

S, A, B, C, D Y

A 2 on the symbol implies a 2 logic module delay on all families except ACT1 and MX.

FamilyModules

Seq Comb

ACT 1/MX 1

Others 2

Input Output

Carry select multiplexer, used in adders

Truth Table

A B S Y

0 X 0 C

1 X 0 D

X 0 1 C

X 1 1 D

Function

Combinational, NAND

S0B S1

D0 , D1, D2, D3, S0A, Y S0B, S1

* A 2 on the symbol implies a 2 logic module delay on all families except ACT 1 and MX.

FamilyModules

Seq Comb

ACT 1/MX 1

Others 2

Input Output

Multiplexer with separate select lines

Truth Table

SOB SOA S1 Y

X 0 0 D0

X 1 0 D1

0 X 1 D2

1 X 1 D3

Function

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input NAND

Truth Table A B Y

Function

NAND2A

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input NAND with active low A-Input

Truth Table A B Y

Function

NAND2B

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input NAND with active low Inputs

Truth Table A B Y

Function

A, B, C Y

* A 2 on the symbol implies 2 logic module delays only for ACT 1 and MX.

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

3-Input NAND

Truth Table A B C Y

X X 0 1

X 0 X 1

0 X X 1

1 1 1 0

Function

NAND3A

A, B, C Y

FamilyModules

Seq Comb

Input Output

Truth Table A B C Y

X X 0 1

X 0 X 1

0 1 1 0

1 X X 1

Function

NAND3B

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input NAND with active low A- and B-Inputs

Truth Table A B C Y

X X 0 1

0 0 1 0

X 1 X 1

1 X X 1

Function

NAND3C

A, B, C Y

FamilyModules

Seq Comb

Input Output

Truth Table A B C Y

0 0 0 0

X X 1 1

X 1 X 1

1 X X 1

Function

A, B, C, D Y

* A 2 on the symbol implies 2 logic module delays except in SX, SX-A, SX-S, and eX.

FamilyModules

Seq Comb

Others 2

Input Output

4-Input NAND

X X X 0 1

X X 0 X 1

X 0 X X 1

0 X X X 1

1 1 1 1 0

Function

NAND4A

A, B, C, D Y

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

X X X 0 1

X X 0 X 1

X 0 X X 1

0 1 1 1 0

1 X X X 1

Function

NAND4B

A, B, C, D Y

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

4-Input NAND with active low A- and B-Inputs

X X X 0 1

X X 0 X 1

0 0 1 1 0

X 1 X X 1

1 X X X 1

Function

NAND4C

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input NAND with active low A-, B- and C-Inputs

X X X 0 1

0 0 0 1 0

X X 1 X 1

X 1 X X 1

1 X X X 1

Function

NAND4D

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

0 0 0 0 0

X X X 1 1

X X 1 X 1

X 1 X X 1

1 X X X 1

Function

NAND5B

A, B, C, D, E Y

FamilyModules

Seq Comb

Input Output

5-input NAND with active low A- and B-inputs

1 X X X X 1

X 1 X X X 1

X X 0 X X 1

X X X 0 X 1

X X X X 0 1

0 0 1 1 1 0

Function

NAND5C

A, B, C, D, E Y

FamilyModules

Seq Comb

All listed 1

Input Output

5-Input NAND with active low A-, B- and C-Inputs

X X X X 0 1

X X X 0 X 1

0 0 0 1 1 0

X X 1 X X 1

X 1 X X X 1

1 X X X X 1

Function

NAND5D

A, B, C, D, E Y

FamilyModules

Seq Comb

All listed 1

Input Output

5-Input NAND with active low A-, B-, C-, and D-Inputs

X X X X 0 1

X X X 1 X 1

X X 1 X X 1

X 1 X X X 1

1 X X X X 1

0 0 0 0 1 0

Function

Axcelerator

Combinational, NOR

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input NOR

Truth Table A B Y

Function

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input NOR with active low A-Input

Truth Table A B Y

Function

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input NOR with active low Inputs

Truth Table A B Y

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input NOR

Truth Table A B C Y

0 0 0 1

X X 1 0

X 1 X 0

1 X X 0

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

Truth Table A B C Y

0 X X 0

1 0 0 1

X X 1 0

X 1 X 0

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input NOR with active low A- and B-Inputs

Truth Table A B C Y

X 0 X 0

0 X X 0

1 1 0 1

X X 1 0

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

Truth Table A B C Y

X X 0 0

X 0 X 0

0 X X 0

1 1 1 1

Function

A, B, C, D Y

* A 2 on the symbol implies 2 logic module delays except SX, SX-A, SX-S, and eX.

FamilyModules

Seq Comb

Others 2

Input Output

4-Input NOR

0 0 0 0 1

X X X 1 0

X X 1 X 0

X 1 X X 0

1 X X X 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

0 X X X 0

1 0 0 0 1

X X X 1 0

X X 1 X 0

X 1 X X 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

X 0 X X 0

0 X X X 0

1 1 0 0 1

X X X 1 0

X X 1 X 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

4-Input NOR with active low A-, B- and C-Inputs

X X 0 X 0

X 0 X X 0

0 X X X 0

1 1 1 0 1

X X X 1 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

X X X 0 0

X X 0 X 0

X 0 X X 0

0 X X X 0

1 1 1 1 1

Function

A, B, C, D, E Y

FamilyModules

Seq Comb

Input Output

0 X X X X 0

X 0 X X X 0

X X 1 X X 0

X X X 1 X 0

X X X X 1 0

1 1 0 0 0 1

Function

Combinational, OR-AND

A, B, C, D, E Y

FamilyModules

Seq Comb

All listed 1

Input Output

5-Input NOR with active low A-, B- and C-Inputs

0 X X X X 0

X 0 X X X 0

X X 0 X X 0

X X X 1 X 0

X X X X 1 0

1 1 1 0 0 1

Function

A, B, C, D, E Y

FamilyModules

Seq Comb

All listed 1

Input Output

5-Input NOR with active low A-, B-, C-, and D-Inputs

X X X X 1 0

X X X 0 X 0

X X 0 X X 0

X 0 X X X 0

0 X X X X 0

1 1 1 1 0 1

Function

Axcelerator

A, B, C Y

FamilyModules

Seq Comb

Input Output

3 Input OR-AND

Truth Table A B C Y

X X 0 0

0 0 X 0

X 1 1 1

1 X 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3 Input OR-AND with active low A-Input

Truth Table A B C Y

X X 0 0

0 X 1 1

1 0 X 0

X 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3 Input OR-AND with active low C-Input

Truth Table A B C Y

0 0 X 0

X 1 0 1

X X 1 0

1 X 0 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3 Input OR-AND with active low A- and C-Inputs

Truth Table A B C Y

0 X 0 1

X X 1 0

1 0 X 0

X 1 0 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

2-wide 4-Input OR-AND

X X 0 0 0

0 0 X X 0

X 1 X 1 1

X 1 1 X 1

1 X X 1 1

1 X 1 X 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

2 wide 4-Input OR-AND with active low A-Input

X X 0 0 0

0 X X 1 1

0 X 1 X 1

1 0 X X 0

X 1 X 1 1

X 1 1 X 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4- Input OR-AND

X X X 0 0

X X 0 X 0

0 0 X X 0

X 1 1 1 1

1 X 1 1 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input OR-AND with active low C-Input

X X X 0 0

0 0 X X 0

X 1 0 1 1

X X 1 X 0

1 X 0 1 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input OR-AND with active low A- and C-Inputs

X X X 0 0

0 X 0 1 1

X X 1 X 0

1 0 X X 0

X 1 0 1 1

Function

Combinational, OR-AND-INVERT

A, B, C, D Y

FamilyModules

Seq Comb

All listed 1

Input Output

4-Input OR-AND

X X X 0 0

0 0 0 X 0

X X 1 1 1

X 1 X 1 1

1 X X 1 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input OR-AND with active low C-Input

X X X 0 0

X X 0 1 1

0 0 1 X 0

X 1 X 1 1

1 X X 1 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input complex OR-AND

0 X X 0 0

0 0 0 X 0

X X 1 1 1

X 1 X 1 1

1 X X X 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input OR-AND-INVERT

Truth Table A B C Y

X X 0 1

0 0 X 1

X 1 1 0

1 X 1 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input OR-AND-INVERT with active low D-Input

0 0 0 X 1

X X 1 0 0

X X X 1 1

X 1 X 0 0

1 X X 0 0

Function

A, B, C, D Y

* A 2 implies 2 logic module delays only for ACT 1 and MX.

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

4 Input OR-AND-INVERT

X X X 0 1

X X 0 X 1

0 0 X X 1

X 1 1 1 0

1 X 1 1 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4 Input OR-AND-INVERT with active low C- and D-Inputs

0 0 X X 1

X 1 0 0 0

X X X 1 1

X X 1 X 1

1 X 0 0 0

Function

Combinational, OR

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input OR

Truth Table A B Y

Function

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input OR with active low A-Input

Truth Table A B Y

Function

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input OR with active low Inputs

Truth Table A B Y

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input OR

Truth Table A B C Y

0 0 0 0

X X 1 1

X 1 X 1

1 X X 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

Truth Table A B C Y

0 X X 1

1 0 0 0

X X 1 1

X 1 X 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input OR with active low A- and B-Inputs

Truth Table A B C Y

X 0 X 1

0 X X 1

1 1 0 0

X X 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

Truth Table A B C Y

X X 0 1

X 0 X 1

0 X X 1

1 1 1 0

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

4-Input OR

0 0 0 0 0

X X X 1 1

X X 1 X 1

X 1 X X 1

1 X X X 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

Input Output

0 X X X 1

1 0 0 0 0

X X X 1 1

X X 1 X 1

X 1 X X 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

X 0 X X 1

0 X X X 1

1 1 0 0 0

X X X 1 1

X X 1 X 1

Function

A, B, C, D Y

*A 2 on the symbol implies 2 logic module delays only for ACT 1 and MX.

FamilyModules

Seq Comb

ACT 1/MX 2

Others 1

Input Output

4-Input OR with active low A-, B- and C-Inputs

X X 0 X 1

X 0 X X 1

0 X X X 1

1 1 1 0 0

X X X 1 1

Function

A, B, C, D Y

* A 2 on the symbol implies 2 logic module delays except for SX, SX-A, SX-S, eX.

FamilyModules

Seq Comb

Others 2

Input Output

X X X 0 1

X X 0 X 1

X 0 X X 1

0 X X X 1

1 1 1 1 0

Function

A, B, C, D, E Y

FamilyModules

Seq Comb

Input Output

5-Input OR with active low A- Input

0 X X X 1 1

X 1 X X X 1

X X 1 X X 1

X X X 1 X 1

X X X X 1 1

1 0 0 0 0 0

Function

A, B, C, D, E Y

FamilyModules

Seq Comb

All listed 1

Input Output

X 0 X X X 1

0 X X X X 1

1 1 0 0 0 0

X X X X 1 1

X X X 1 X 1

X X 1 X X 1

Function

A, B, C, D, E Y

FamilyModules

Seq Comb

Input Output

5-Input OR with active low A-, B- and C-Inputs

0 X X X X 1

X 0 X X X 1

X X 0 X X 1

X X X 1 X 1

X X X X 1 1

1 1 1 0 0 0

Function

QCLKINT

NOTE: QCLKINT does not use any modules

For more information on the Global Clock Network, refer to Actel’s Data Book.

Input Output

Truth Table A Y

Function

3200DX, MX, SX-A, SX-S

QCLKINTI

NOTE: QCLKINTI does not use any modules

For more information on the Global Clock Network, refer to Actel’s Data Book.

Input Output

Truth Table A Y

Function

SX-A, SX-S

CLRCLK

CLR, T, CLK Q

FamilyModules

Seq Comb

All listed 1

Input Output

T-Type Flip-Flop with active low Clear

Truth Table CLR T CLK Qn+1

0 X X 0

1 1 ↑ !Q

1 0 ↑ Q

Function

CLRCLK

CLR, T, CLK Q

FamilyModules

Seq Comb

All listed 1

Input Output

T-Type Flip-Flop with active low Clear and Clock

Truth Table

CLR T CLK Qn+1

0 X X 0

1 1 ↓ !Q

1 0 ↓ Q

Function

NOTE: VCC does not use any modules.

Input Output

Power Function

Combinational, XOR-AND

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input XOR-AND

Truth Table A B C Y

X X 0 0

0 0 X 0

0 1 1 1

1 0 1 1

1 1 X 0

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input XNOR-AND

Truth Table A B C Y

X X 0 0

0 0 1 1

0 1 X 0

1 0 X 0

1 1 1 1

Function

Combinational, XNOR-AND

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input XNOR-AND with active low C-input

Truth Table A B C Y

X X 1 0

0 0 X 0

1 0 0 1

0 1 0 1

1 1 X 0

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input XNOR-AND with active low C-input

Truth Table A B C Y

X X 1 0

0 0 0 1

1 0 X 0

0 1 X 0

1 1 0 1

Function

Combinational, XNOR-NAND

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input XNOR-NAND

Truth Table A B C Y

X X 0 1

0 0 X 1

1 0 1 0

0 1 1 0

1 1 X 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input XNOR-NAND

Truth Table A B C Y

X X 0 1

0 0 1 0

1 0 X 1

0 1 X 1

1 1 1 0

Function

Combinational, XNOR

A, B Y

FamilyModules

Seq Comb

Input Output

2- Input XNOR

Truth Table A B Y

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input XNOR

Truth Table A B C Y

0 0 0 1

1 0 0 0

0 1 0 0

1 1 0 1

0 0 1 0

1 0 1 1

0 1 1 1

Function

Combinational, XOR-OR

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input XOR-OR

Truth Table A B C Y

0 0 0 0

X X 1 1

0 1 X 1

1 0 X 1

1 1 0 0

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input XNOR-OR

Truth Table

A B C Y

0 0 0 1

X X 1 1

0 1 0 0

1 0 0 0

1 1 0 1

Function

Combinational, XOR

A, B Y

FamilyModules

Seq Comb

Input Output

2-Input XOR

Truth Table

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input XOR

Truth Table A B C Y

0 0 0 0

1 0 0 1

0 1 0 1

1 1 0 0

0 0 1 1

1 0 1 0

0 1 1 0

1 1 1 1

Function

A, B, C, D Y

FamilyModules

Seq Comb

All listed 2

Input Output

4-Input Exclusive OR Gate

0 0 0 0 0

0 0 0 1 1

0 0 1 0 1

0 0 1 1 0

0 1 0 0 1

0 1 0 1 0

0 1 1 0 0

0 1 1 1 1

1 0 0 0 1

1 0 0 1 0

1 0 1 0 0

1 0 1 1 1

1 1 0 0 0

1 1 0 1 1

1 1 1 0 1

1 1 1 1 0

Function

Axcelerator

A, B, C, D Y

FamilyModules

Seq Comb

All listed 2

Input Output

4-input Exclusive NOR gate

0 0 0 0 1

0 0 0 1 0

0 0 1 0 0

0 0 1 1 1

0 1 0 0 0

0 1 0 1 1

0 1 1 0 1

0 1 1 1 0

1 0 0 0 0

1 0 0 1 1

1 0 1 0 1

1 0 1 1 0

1 1 0 0 1

1 1 0 1 0

1 1 1 0 0

1 1 1 1 1

Function

Axcelerator

Combinational, Gate

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input function

Truth Table A B C Y

0 0 0 1

1 0 0 0

0 1 0 0

1 1 0 0

0 0 1 0

1 0 1 0

0 1 1 0

1 1 1 1

Function

A, B, C Y

FamilyModules

Seq Comb

Input Output

3-Input function

Truth Table A B C Y

0 0 0 0

1 0 0 1

0 1 0 1

1 1 0 1

0 0 1 1

1 0 1 1

0 1 1 1

1 1 1 0

Function

CC-Module Flip Flops

These macros are useful in some radiation hostile applications. They sacri-fice area in exchange for a lower single-event upset (SEU) rate caused by ion particle collisions. These special cells use two combinational modules to implement a register instead of using the dedicated registers in the array. (See the application note titled, Design Techniques for RadHard Field Programmable Gate Arrays.)

DF1_CC

D, CLK Q

FamilyModules

Seq Comb

Input Output

D-Type Flip-Flop

Truth Table CLK Qn+1

Function

ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX

DF1A_CC

D, CLK QN

FamilyModules

Seq Comb

All listed 2

Input Output

D-Type Flip-Flop with active low Output

Truth Table CLK QNn+1

↑ !D

Function

DF1B_CC

D, CLK Q

FamilyModules

Seq Comb

ACT 2, ACT 3, 3200DX, MX 2

Input Output

D-Type Flip-Flop with active low Clock

Truth Table CLK Qn+1

Function

ACT 2, ACT 3, 3200DX, MX SX, SX-A, SX-S, eX

DF1C_CC

D, CLK QN

FamilyModules

Seq Comb

ACT 2, ACT3, 3200DX, MX 2

Input Output

D-Type Flip-Flop with active low Clock and Output

Truth Table CLK QNn+1

↓ !D

Function

DFC1_CC

D, CLK, CLR Q

FamilyModules

Seq Comb

ACT 2, ACT 3, 3200DX, MX 2

Input Output

D-Type Flip-Flop, with active high Clear

Truth Table CLR CLK Qn+1

0 ↑ D

Function

DFC1A_CC

D, CLK, CLR Q

FamilyModules

Seq Comb

ACT 2, ACT 3, 3200DX, MX 2

Input Output

D-Type Flip-Flop, with active high Clear, and active low Clock

0 ↓ D

Function

DFC1B_CC

D, CLK, CLR Q

FamilyModules

Seq Comb

All listed 2

Input Output

D-Type Flip-Flop, with active low Clear

1 ↑ D

Function

DFC1D_CC

D, CLK, CLR Q

FamilyModules

Seq Comb

Input Output

D-Type Flip-Flop, with active low Clear and Clock

1 ↓ D

Function

DFE_CC

D, E, CLK Q

FamilyModules

Seq Comb

Input Output

D-Type Flip-Flop with active high Enable

Truth Table E CLK Qn+1

1 ↑ D

Function

DFE1B_CC

D, E, CLK Q

FamilyModules

Seq Comb

Input Output

0 ↑ D

Function

DFE1C_CC

D, E, CLK Q

FamilyModules

Seq Comb

Input Output

D-Type Flip-Flop with active low Enable and Clock

0 ↓ D

Function

DFEA_CC

D, E, CLK Q

FamilyModules

Seq Comb

Input Output

D-Type Flip-Flop with Enable and active low Clock

1 ↓ D

Function

DFM_CC

A, B, S, CLK Q

FamilyModules

Seq Comb

All listed 2

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data

Truth Table S CLK Qn+1

0 ↑ A

1 ↑ B

Function

DFMA_CC

A, B, S, CLK Q

FamilyModules

Seq Comb

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active low Clock

Truth Table S CLK Qn+1

0 ↓ A

1 ↓ B

Function

DFM1B_CC

A, B, S, CLK QN

FamilyModules

Seq Comb

All listed 2

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data, and active low Output

Truth Table S CLK QNn+1

0 ↑ !A

1 ↑ !B

Function

DFM1C_CC

A, B, S, CLK QN

FamilyModules

Seq Comb

All listed 2

Input Output

D-Type Flip-Flop with 2-input Multiplexed Data and active low Clock and Output

Truth Table S CLK QNn+1

0 ↓ !A

1 ↓ !B

Function

DFP1_CC*

D, PRE, CLK Q

* Identical to macro DFP1.

FamilyModules

Seq Comb

ACT 2, ACT 3, 3200DX, MX 2

Input Output

D-Type Flip-Flop with active high Preset

Truth Table PRE CLK Qn+1

0 ↑ D

Function

DFP1A_CC*

D, PRE, CLK Q

* Identical to macro DFP1A.

FamilyModules

Seq Comb

ACT 2, ACT 3, 3200DX, MX 2

Input Output

D-Type Flip-Flop with active high Preset, and active low Clock

Truth Table

PRE CLK Qn+1

0 ↓ D

Function

DFP1B_CC*

D, PRE, CLK Q

* Identical to macro DFP1B.

FamilyModules

Seq Comb

Input Output

D-Type Flip-Flop with active low Preset

Truth Table

PRE CLK Qn+1

1 ↑ D

Function

DFP1D_CC*

D, PRE, CLK Q

* Identical to macro DFP1D.

FamilyModules

Seq Comb

ACT 2, ACT 3, 3200DX, MX 2

Input Output

D-Type Flip-Flop with active low Preset and Clock

Truth Table

PRE CLK Qn+1

1 ↓ D

Function

DFPC_CC*

CLRCLK

CLR, D, PRE, CLK Q

* Identical to macro DFPC.

FamilyModules

Seq Comb

ACT 2, ACT 3, 3200DX, MX 2

Input Output

D-Type Flip-Flop with active high Preset, active low Clear, and active high Clock

Truth Table

CLR PRE CLK Qn+1

0 X X 0

1 1 X 1

1 0 ↑ D

Function

DFPCA_CC*

CLRCLK

CLR, D, PRE, CLK Q

* Identical to Macro DFPCA.

** Your design should not allow both PRE and CLR to be asserted at the same time.

FamilyModules

Seq Comb

ACT 2, ACT 3, 3200DX, MX 2

Input Output

D-Type Flip-Flop with active high Preset, active low Clear, and active low Clock

Truth Table

CLR PRE CLK Qn+1

0 0 X 0

1 1 X 1

1 0 ↓ D

0 1 X **

Function

Memory Macros

RAM Macros

RAM4FA

RDAD5RDAD4RDAD3READ2RDAD1RDAD0

WD3WD2WD1WD0

WRAD5WRAD4WRAD3WRAD2WRAD1WRAD0

WENBLKENBLKENS

RD3RD2RD1RD0

Function64X4 dual-port RAM with falling Write clock and asynchronous

3200DX, MX

Truth Table

NOTE 1: RDAD contents always appear at RD.

NOTE 2: BLKENS must be driven by a GND or VCC macro.

NOTE 3: The use of ACTgen RAM blocks is recommended over direct use of RAM macros because ACTgen includes buffering to achieve optimal performance.

WCLK BLKEN WEN Action

↓ BLKENS 1 WD written to WRAD

0 X X none

1 X X none

X !BLKENS X none

X X 0 none

InputRDAD5, RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, WD3, WD2, WD1, WD0, WRAD5, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK

OutputRD3, RD2, RD1, RD0

FamilyModules

All listed 1

RAM4FF

RENRCLK

WD3WD2WD1WD0

WENBLKENBLKENS

RD3RD2RD1RD0

Function64X4 dual-port RAM with falling Write clock and falling Read clock

3200DX, MX

Write Truth Table

Read Truth Table

0 X X none

1 X X none

X !BLKENS X none

X X 0 none

RCLK REN Action

↓ 1 RDAD contents appear at RD

0 X RD is unchanged

1 X RD is unchanged

X 0 RD is unchanged

InputRDAD5, RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD3, WD2, WD1, WD0, WRAD5, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK

FamilyModules

All listed 1

RAM4FR

RENRCLK

WD3WD2WD1WD0

WENBLKENBLKENS

RD3RD2RD1RD0

Function64X4 dual-port RAM with falling Write clock and rising Read clock

3200DX, MX

Write Truth Table

Read Truth Table

0 X X none

1 X X none

X !BLKENS X none

X X 0 none

RCLK REN Action

↑ 1 RDAD contents appear at RD

0 X RD is unchanged

1 X RD is unchanged

X 0 RD is unchanged

InputRDAD5, RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD3, WD2, WD1, WD0, WRAD5, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK

FamilyModules

All listed 1

RAM4RA

WD3WD2WD1WD0

WENBLKENBLKENS

RD3RD2RD1RD0

Function64X4 dual-port RAM with rising Write clock and asynchronous

3200DX, MX

Write Truth Table

↑ BLKENS 1 WD written to WRAD

0 X X none

1 X X none

X !BLKENS X none

X X 0 none

InputRDAD5, RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, WD3, WD2, WD1, WD0, WRAD5, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK

FamilyModules

All listed 1

RAM4RF

RENRCLK

WD3WD2WD1WD0

WENBLKENBLKENS

RD3RD2RD1RD0

Function64X4 dual-port RAM with rising Write clock and falling Read clock

3200DX, MX

Write Truth Table

Read Truth Table

0 X X none

1 X X none

X !BLKENS X none

X X 0 none

RCLK REN Action

0 X RD is unchanged

1 X RD is unchanged

X 0 RD is unchangedInputRDAD5, RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD3, WD2, WD1, WD0, WRAD5, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK

FamilyModules

All listed 1

RAM4RR

RENRCLK

WD3WD2WD1WD0

WENBLKENBLKENS

RD3RD2RD1RD0

Function64X4 dual-port RAM with rising Write clock and rising Read clock

Actel recommends that you do NOT use this macro. Contact Actel technical supoort for more information.

3200DX, MX

Write Truth Table

Read Truth Table

0 X X none

1 X X none

X !BLKENS X none

X X 0 none

RCLK REN Action

0 X RD is unchanged

1 X RD is unchanged

X 0 RD is unchangedInputRDAD5, RDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD3, WD2, WD1, WD0, WRAD5, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK

FamilyModules

All listed 1

RAM8FA

RDAD4RDAD3READ2RDAD1RDAD0

WD7WD6WD5WD4WD3WD2WD1WD0

WRAD4WRAD3WRAD2WRAD1WRAD0

WENBLKENBLKENS

RD7RD6RD5RD4RD3RD2RD1RD0

Function32X8 dual-port RAM with falling Write clock and asynchronous

3200DX, MX

Write Truth Table

0 X X none

1 X X none

X !BLKENS X none

X X 0 none

InputRDAD4, RDAD3, RDAD2, RDAD1, RDAD0, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK

OutputRD7, RD6, RD5, RD4, RD3, RD2, RD1, RD0

FamilyModules

All listed 1

RAM8FF

RENRCLK

WENBLKENBLKENS

Function32X8 dual-port RAM with falling Write clock and falling Read clock

3200DX, MX

Write Truth Table

Read Truth Table

0 X X none

1 X X none

X !BLKENS X none

X X 0 none

RCLK REN Action

0 X RD is unchanged

1 X RD is unchanged

X 0 RD is unchangedInputRDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK

FamilyModules

All listed 1

RAM8FR

RENRCLK

WENBLKENBLKENS

Function32X8 dual-port RAM with falling Write clock and rising Read clock

3200DX, MX

Write Truth Table

Read Truth Table

0 X X none

1 X X none

X !BLKENS X none

X X 0 none

RCLK REN Action

0 X RD is unchanged

1 X RD is unchanged

FamilyModules

All listed 1

RAM8RA

WENBLKENBLKENS

Function32X8 dual-port RAM with rising Write clock and asynchronous

3200DX, MX

Write Truth Table

0 X X none

1 X X none

X !BLKENS X none

X X 0 none

InputRDAD4, RDAD3, RDAD2, RDAD1, RDAD0, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK

FamilyModules

All listed 1

RAM8RF

RENRCLK

WENBLKENBLKENS

Function32X8 dual-port RAM with rising Write clock and falling Read clock

3200DX, MX

Write Truth Table

Read Truth Table

0 X X none

1 X X none

X !BLKENS X none

X X 0 none

RCLK REN Action

0 X RD is unchanged

1 X RD is unchanged

FamilyModules

All listed 1

RAM8RR

RENRCLK

WENBLKENBLKENS

Function32X8 dual-port RAM with rising Write clock and rising Read clock

3200DX, MX

Write Truth Table

Read Truth Table

0 X X none

1 X X none

X !BLKENS X none

X X 0 none

RCLK REN Action

0 X RD is unchanged

1 X RD is unchanged

X 0 RD is unchanged

InputRDAD4, RDAD3, RDAD2, RDAD1, RDAD0, REN, RCLK, WD7, WD6, WD5, WD4, WD3, WD2, WD1, WD0, WRAD4, WRAD3, WRAD2, WRAD1, WRAD0, WEN, BLKEN, BLKENS, WCLK

FamilyModules

All listed 1

RAM64K36 /RAM64K36P

RDAD11RDAD10......RDAD0

RD35RD34......RD0

WRAD11WRAD10......WRAD0

WD35WD34......WD0

DEPTH3...DEPTH0

WENRENWCLKRCLKWW2WW1WW0RW2RW1RW0

FunctionDual port completely independent fully synchronous RAM; the

RAM blocks may be cascaded up to 16 by configuring the Depth3-0 ports.

Actel recommends you use ACTgen RAM blocks instead of RAM macros because ACTgen configures WW/RW to choose the best aspect ratio and cascades multiple blocks to achieve larger configu-rations.

For RAM64K36P, data appears on RD after 2 clock cycles on RCLK

Axcelerator

Write Truth Table

Read Truth Table

WCLK WEN Action

1 1 WD written to WRAD

0 1 None

X 0 None

RCLK REN Action

1 1 RD is read from RDAD

0 1 RD is unchanged

X 0 Rd is unchanged

InputRDAD11, ..., RDAD0WRAD11, ..., WRAD0WD35, ..., WD0, WEN, REN, WCLK, RCLK, WW2, WW1, WW0, RW2, RW1, RW0, DEPTH3, ..., DEPTH0

OutputRD35, ..., RD0

Family

Modules

All listed 1

SRAM Port Aspect Ratios

Read/Write Depth

Read/Write ADDR Bus

Read/Write Data Bus RW/WW[2:0]

1 4096 ADDR[11:0] DATA[0] 000

2 2048 ADDR[10:0] DATA[1:0] 001

4 1024 ADDR[9:0] DATA[3:0] 010

9 512 ADDR[8:0] DATA[8:0] 011

18 256 ADDR[7:0] DATA[17:0] 100

36 128 ADDR[6:0] DATA[35:0] 101

FIFO Macros

FIFO64K36/FIFO64K36P

RD35RD34......RD0

FULLEMPTYAFULL

AEMPTY

AFVAL7AFVAL6......AFVAL0

AEVAL7AEVAL6......AEVAL0

WD35WD34......WD0

DEPTH3...DEPTH0

WIDTH2...WIDTH0

WCLKRCLKWENRENCLR

FunctionDual port completely independent fully synchronous FIFO

For FIFO64K36P, data appears on READ after 2 clock cycles on RCLK. FIFO flag behavior is same as that of FIFO64K36

Axcelerator

See the Axcelerator datasheet at http://www.actel.com for more information on this macro.

InputWD35, ..., WD0, AFVAL7, ..., AFVAL0, AEVAL7, ..., AEVAL0, WCLK, RCLK, WEN, REN, CLR, WIDTH2, ..., WIDTH0 DEPTH3, ..., DEPTH0

OutputRD35, ..., RD0FULL, EMPTY, AFULL, AEMPTY

Family

Modules

All listed 1

FIFO Aspect Ratios Table 1

Data Width FIFO Depth Read/Write Data Bus Width[2:0]

1 4096 DATA[0] 000

2 2048 DATA[1:0] 001

4 1024 DATA[3:0] 010

9 512 DATA[8:0] 011

18 256 DATA[17:0] 100

36 128 DATA[35:0] 101

FIFO Aspect Ratios Table 2

Depth Cascaded Blocks Fulla

a. W = width in FIFO Aspect Ratios Table 1

Address Bus WCNT/RCNT AEVAL/AFVAL Step Size

00001 1 212-W [15:W] 28-W

00011 2 213-W [15:W] 28-W

00111 4 214-W [15:W] 28-W

01111 8 215-W [15:W] 28-W

11111 16 216-W [15:W] 28-W

I/O Macros

Input/Output, General Use

D PADE

D, E, PAD PAD, Y

FamilyModules

Seq I/O

Input Output

Bidirectional Buffer, High Slew (with Hidden Buffer at Y pin)

Truth Table

MODE E D PAD Y

OUTPUT 1 X D D

INPUT 0 X X PAD

Function

CLKBIBUF

D, E, PAD PAD, Y

NOTE: Refer to the device-specific datasheet for more Clock Network information.

FamilyModules

Seq I/O

All listed 1

Input Output

Bidirectional with input dedicated to hardwired clock network

Truth Table

D E PAD Y

X 0 Z X

X 0 0 0

X 0 1 1

0 1 0 0

1 1 1 1

Function

ACT1, ACT2, ACT3, 3200DX, 42MX, 54SX, 54SX-A, Axcelerator

HCLKBIBUF

D, E, PAD PAD, Y

FamilyModules

Seq I/O

All listed 1

Input Output

Bidirectional with input dedicated to hardwired clock network

HCLKs (hardwired clocks) can drive only the CLK pins of the dedicated R-Cells, RAM Clock Pins (Read and Write) and IO-REG Clock Pins. The HCLKs cannot drive any other pins of R-Cells, or any pins of C-cells; this rules out CC-Flipflops as well.

Truth Table

D E PAD Y

X 0 Z X

X 0 0 0

X 0 1 1

0 1 0 0

1 1 1 1

Function

ACT1, ACT2, ACT3, 3200DX, 42MX, 54SX, 54SX-A, Axcelerator

CLKBIBUFI

D, E, PAD PAD, Y

FamilyModules

Seq I/O

SX-A, SX-S 1

Input Output

Biderctional with inverted Input Dedicated to routed Clock Network

The CLKBIBUFI macro is intended for the SX72-A and SX72-S devices.

Truth Table

D E PAD Y

X 0 Z X

X 0 0 1

X 0 1 0

0 1 0 1

1 1 1 0

Function

SX-A, SX-S

CLKBUF

NOTE 1: For an internal Clock net, refer to the CLKINT macro.

NOTE 2: Refer to Actel’s Databook for more Clock Network information.

FamilyModules

Seq I/O

Input Output

Input for Dedicated Routed Clock Network

Truth Table

Function

CLKBUFI

NOTE 1: For an internal Clock net, refer to the CLKINTI macro.

FamilyModules

Seq I/O

Input Output

Inverting Input for Dedicated Routed Clock Network

Truth Table

Function

SX, SX-A, SX-S, eX

HCLKBUF

NOTE: Refer to Actel’s Databook for more Clock Network information.

FamilyModules

Seq I/O

All listed 1

Input Output

Dedicated high-speed S-Module Clock Buffer

Truth Table

Function

ACT 3, SX, SX-A, SX-S, eX, Axcelerator

FamilyModules

Seq I/O

All listed 1

Input Output

Input Buffer

Truth Table

Function

OUTBUF

FamilyModules

Seq I/O

Input Output

Output Buffer, High Slew

Truth Table

Function

QCLKBIBUFI

D, E, PAD PAD, Y

FamilyModules

Seq I/O

SX-A, SX-S 1

Input Output

Biderctional with inverted Input Dedicated to routed Clock Network

The QCLKBIBUFI macro is intended for the SX72-A and SX72-S devices.

Truth Table

D E PAD Y

X 0 Z X

X 0 0 1

X 0 1 0

0 1 0 1

1 1 1 0

Function

SX-A, SX-S

QCLKBIBUF

D, E, PAD PAD, Y

FamilyModules

Seq I/O

SX-A, SX-S 1

Input Output

Biderctional with Input Dedicated to routed Clock Network

The QCLKBIBUF macro is intended for the SX72-A and SX72-S devices.

Truth Table

D E PAD Y

X 0 Z X

X 0 0 0

X 0 1 1

0 1 0 0

1 1 1 1

Function

SX-A, SX-S

QCLKBUF

FamilyModules

Seq I/O

All listed 1

Input Output

Input for Dedicated Routed Clock Network

Truth Table

Function

3200DX, MX , SX-A, SX-S

QCLKBUFI

FamilyModules

Seq I/O

SX-A, SX-S 1

Input Output

Inverted Input for Dedicated Routed Clock Network

The QCLKBUFI macro is intended for the SX72-A and SX72-S devices.

Truth Table

Function

SX-A, SX-S

TRIBUFF

D PADE

D, E PAD

NOTE: Refer to Actel’s Databook for internal tristate implementation using multiplexers.

FamilyModules

Seq I/O

Input Output

Tristate Output, High Slew

Truth Table

Function

ACT 1, ACT 2, ACT 3, 3200DX, MX, SX, SX-A, SX-S, eX

ACT 2/XL/DX/MX I/O Macros

BBDLHS

HIGH SLEW

D, E, GOUT, GIN, PAD PAD, Q

FamilyModules

Seq I/O

All listed 1

Input Output

Bidirectional with Input Latch and Output Latch

Truth Table

MODE E GOUT GIN PAD Q

OUTPUT1 0 1 PADn-1 Qn-1

1 1 0 D D

INPUT0 X 1 X Qn-1

0 X 0 X PAD

TRISTATE 0 X X Z X

Function

ACT 2, 3200DX, MX

HIGH SLEW

D, E, PAD PAD, Y

NOTE: For new designs, instead of BBHS we recommend that you use “BIBUF” on page 256.

FamilyModules

Seq I/O

All listed 1

Input Output

Bidirectional Buffer, High Slew

Truth Table

MODE E PAD Y

OUTPUT 1 D D

INPUT 0 X PAD

Function

G, PAD Q

FamilyModules

Seq I/O

All listed 1

Input Output

Input Buffer with Input Latch, with active low Clock

Truth Table

1 Qn-1

Function

ACT 2, 3200DX, MX

PAD, CLK Q

FamilyModules

Seq I/O

All listed 1 1

Input Output

Input Register

Truth Table

↑ PAD

Function

ACT 2, 3200DX, MX

PAD, CLK QN

FamilyModules

Seq I/O

All listed 1 1

Input Output

Input register with active Low output

Truth Table

CLK QN

↑ !PAD

Function

ACT 2, 3200DX, MX

OBDLHS

HIGH SLEW

D, G PAD

FamilyModules

Seq I/O

All listed 1

Input Output

Output Buffer with Output Latch, High Slew

Truth Table

0 PADn-1

Function

ACT 2, 3200DX, MX

HIGH SLEW

NOTE: For new designs, instead of OBHS we recommend that you use “OUTBUF” on page 260.

FamilyModules

Seq I/O

All listed 1

Input Output

Output Buffer, High Slew

Truth Table

Function

D, CLK PAD

FamilyModules

Seq I/O

All listed 1 1

Input Output

Output Register, High Slew

Truth Table

CLK PADn+1

Function

ACT 2, 3200DX, MX

D, CLK PAD

FamilyModules

Seq I/O

All listed 1 1

Input Output

Inverted Output Register, High Slew

Truth Table

CLK PADn+1

↑ !D

Function

ACT 2, 3200DX, MX

HIGH SLEW

D, E, CLK PAD

FamilyModules

Seq I/O

All listed 1 1

Input Output

Inverted Output Register, Tristate Enable, High Slew

Truth Table

E CLK PADn+1

1 ↑ !D

Function

ACT 2, 3200DX, MX

HIGH SLEW

D, E, CLK PAD

FamilyModules

Seq I/O

All listed 1 1

Input Output

Output Register, Tristate Enable, High Slew

Truth Table

E CLK PADn+1

1 ↑ D

Function

ACT 2, 3200DX, MX

TBDLHS

HIGH SLEW

D, E, G PAD

FamilyModules

Seq I/O

All listed 1

Input Output

Tristate Output with Latch, High Slew

Truth Table

E G PAD

1 0 PADn-1

Function

ACT 2, 3200DX, MX

HIGH SLEW

D, E PAD

NOTE: For new designs, instead of TBHS we recommend that you use “TRIBUFF” on page 263.

FamilyModules

Seq I/O

All listed 1

Input Output

Tristate Output, High Slew

Truth Table

Function

ACT 3 I/O Macros

HIGH SLEW

D, E, IDE, PAD PAD, Y

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional buffer with AND gate, High Slew

Truth Table

MODE E IDE PAD Y

OUTPUT1 1 D D

1 0 D 0

INPUT0 1 X PAD

0 0 X 0

Function

LOW SLEW

D, E, IDE, PAD PAD, Y

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional buffer with AND gate, Low Slew

Truth Table

MODE E IDE PAD Y

OUTPUT1 1 D D

1 0 D 0

INPUT0 1 X PAD

0 0 X 0

Function

BBUFTH

HIGH SLEW

D, E, PAD PAD, Y

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Buffer, Tristate Enable, High Slew

Truth Table

MODE E PAD Y

OUTPUT 1 D D

INPUT 0 X PAD

Function

BBUFTL

LOW SLEW

D, E, PAD PAD, Y

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Buffer, Tristate Enable, Low Slew

Truth Table

MODE E PAD Y

OUTPUT 1 D D

INPUT 0 X PAD

Function

BIECTH

HIGH SLEW

D, E, IDE, CLK, IOPCL, PAD, Q PAD

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Input Register with Clear, Input Data Enable, Tristate Enable, High Slew

Truth Table

MODE E IOPCL IDE CLK PAD Q

OUTPUT

1 0 X X D 0

1 1 0 ↑ D D

1 1 1 ↑ D Qn-1

0 0 X X X 0

0 1 0 ↑ X PAD

0 1 1 ↑ X Qn-1

Function

BIECTL

LOW SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Input Register with Clear, Input Data Enable, Tristate Enable, Low Slew

Truth Table

OUTPUT

1 0 X X D 0

1 1 0 ↑ D D

1 1 1 ↑ D Qn-1

0 0 X X X 0

0 1 0 ↑ X PAD

0 1 1 ↑ X Qn-1

Function

BIEPTH

HIGH SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Input Register with Preset, Input Data Enable, Tristate Enable, High Slew

Truth Table

OUTPUT

1 0 X X D 1

1 1 0 ↑ D D

1 1 1 ↑ D Qn-1

0 0 X X X 1

0 1 0 ↑ X PAD

0 1 1 ↑ X Qn-1

Function

BIEPTL

LOW SLEW

D, E, IDE, CLK, IOPCL, PAD, QPAD

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Input Register with Preset, Input Data Enable, Tristate Enable, Low Slew

Truth Table

OUTPUT

1 0 X X D 1

1 1 0 ↑ D D

1 1 1 ↑ D Qn-1

0 0 X X X 1

0 1 0 ↑ X PAD

0 1 1 ↑ X Qn-1

Function

BRECTH

HIGH SLEW

D, E, ODE, CLK, IOPCL, PAD, Y PAD

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Output Register, with Clear, Output Data Enable, Tristate Enable, High Slew

Truth Table

MODE E IOPCL ODE CLK PAD Y

OUTPUT

1 0 X X 0 0

1 1 1 ↑ PADn-1 Yn-1

1 1 0 ↑ D D

INPUT 0 X X X X PAD

Function

BRECTL

LOW SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Output Register, with Clear, Output Data Enable, Tristate Enable, Low Slew

Truth Table

OUTPUT

1 0 X X 0 0

1 1 1 ↑ PADn-1 Yn-1

1 1 0 ↑ D D

INPUT 0 X X X X PAD

Function

BREPTH

HIGH SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Output Register, with Preset, Output Data Enable, Tristate Enable, High Slew

Truth Table

OUTPUT

1 0 X X 1 1

1 1 1 ↑ PADn-1 Yn-1

1 1 0 ↑ D D

INPUT 0 X X X X PAD

Function

BREPTL

LOW SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Output Register, with Preset, Output Data Enable, Tristate Enable, Low Slew

Truth Table

OUTPUT

1 0 X X 1 1

1 1 1 ↑ PADn-1 Yn-1

1 1 0 ↑ D D

INPUT 0 X X X X PAD

Function

DECETHHIGH SLEW

CLRCLK

CLKCLR

D, E, IDE, CLK, IOPCL, PAD, Q PAD, ODE

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Double Registered, with Clear, Input Data Enable, Tristate Enable, High Slew, Output Data Enable

Truth Table

MODE E IOPCL ODE IDE CLK PAD Q

OUTPUT

1 0 X X X 0 0

1 1 0 0 ↑ D PAD

1 1 1 1 X PADn-1 Qn-1

0 0 X X X X 0

0 1 X 0 ↑ X PAD

0 1 X 1 X X Qn-1

Function

DECETL

CLRCLK

CLKCLR

LOW SLEW

D, E, ODE, CLK, IOPCL, PAD, Q IDE, PAD

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Double Registered, with Clear, Input Data Enable, Tristate Enable, Low Slew, Output Data Enable

Truth Table

OUTPUT

1 0 X X X 0 0

1 1 0 0 ↑ D PAD

1 1 1 1 X PADn-1 Qn-1

0 0 X X X X 0

0 1 X 0 ↑ X PAD

0 1 X 1 X X Qn-1

Function

DEPETH

HIGH SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Double Registered, with Preset, Input Data Enable, Tristate Enable, High Slew, Output Data Enable

Truth Table

OUTPUT

1 0 X X X 1 1

1 1 0 0 ↑ D PAD

1 1 1 1 X PADn-1 Qn-1

0 0 X X X X 1

0 1 X 0 ↑ X PAD

0 1 X 1 X X Qn-1

Function

DEPETL

LOW SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Bidirectional Double Registered, with Preset, Input Data Enable, Tristate Enable, Low Slew, Output Data Enable

Truth Table

OUTPUT

1 0 X X X 1 1

1 1 0 0 ↑ D PAD

1 1 1 1 X PADn-1 Qn-1

0 0 X X X X 1

0 1 X 0 ↑ X PAD

0 1 X 1 X X Qn-1

Function

HIGH SLEW

D, E, ODE, CLK, PAD, Y IOPCL, PAD

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Register with feedback, Clear, Output Data Enable, Tristate Enable, High Slew

Truth Table

E IOPCL ODE CLK Y PAD

1 0 X X 0 0

1 1 0 ↑ D D

1 1 1 X Yn-1 PADn-1

0 0 X X 0 Z

0 1 0 ↑ D Z

0 1 1 X Yn-1 Z

Function

LOW SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Register with feedback, Clear, Output Data Enable, Tristate Enable, Low Slew

Truth Table

1 0 X X 0 0

1 1 0 ↑ D D

1 1 1 X Yn-1 PADn-1

0 0 X X 0 Z

0 1 0 ↑ D Z

0 1 1 X Yn-1 Z

Function

HIGH SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Register with feedback, Preset, Output Data Enable, Tristate Enable, High Slew

Truth Table

1 0 X X 1 1

1 1 0 ↑ D D

1 1 1 X Yn-1 PADn-1

0 0 X X 1 Z

0 1 0 ↑ D Z

0 1 1 X Yn-1 Z

Function

LOW SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Register with feedback, Preset, Output Data Enable, Tristate Enable, Low Slew

Truth Table

1 0 X X 1 1

1 1 0 ↑ D D

1 1 1 X Yn-1 PADn-1

0 0 X X 1 Z

0 1 0 ↑ D Z

0 1 1 X Yn-1 Z

Function

FECTMH

HIGH SLEW

D, E, ODE, CLK, PAD, Y IOPCL, PAD, M

NOTE: When M = 0, LSB is selected. When M = 1, MSB is selected.

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Register with Muxed Feedback, Clear, Output Data Enable, Tristate Enable, High Slew

Truth Table

MODE E IOPCL ODE CLK PAD M Y

OUTPUT

1 0 X X 0 X 0

1 1 0 ↑ D X D

1 1 1 X PADn-1 X Yn-1

INPUT0 1 0 ↑ X 0 D

0 1 X X X 1 PAD

Function

FECTML

LOW SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Register with Muxed Feedback, Clear, Output Data Enable, Tristate Enable, Low Slew

Truth Table

OUTPUT

1 0 X X 0 X 0

1 1 0 ↑ D X D

1 1 1 X PADn-1 X Yn-1

INPUT0 1 0 ↑ X 0 D

0 1 X X X 1 PAD

Function

FEPTMH

HIGH SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Register with Muxed Feedback, Preset, Output Data Enable, Tristate Enable, High Slew

Truth Table 1

OUTPUT

1 0 X X 1 X 1

1 1 0 ↑ D X D

1 1 1 X PADn-1 X Yn-1

INPUT0 1 0 ↑ X 0 D

0 1 X X X 1 PAD

1.NOTE: When M = 0, LSB is selected. When M = 1, MSB is selected.

Function

FEPTMLLOW SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Register with Muxed Feedback, Preset, Output Data Enable, Tristate Enable, Low Slew

Truth Table 1

OUTPUT

1 0 X X 1 X 1

1 1 0 ↑ D X D

1 1 1 X PADn-1 X Yn-1

INPUT0 1 0 ↑ X 0 D

0 1 X X X 1 PAD

1.NOTE: When M = 0, LSB is selected. When M = 1, MSB is selected.

Function

FamilyModules

Seq I/O

ACT 3 1

Input Output

Input Buffer

Truth Table

Function

IOCLKBUF

FamilyModules

Seq I/O

ACT 3 1

Input Output

Dedicated I/O Module Clock Buffer

Truth Table

Function

IOPCLBUF

FamilyModules

Seq I/O

ACT 3 1

Input Output

Dedicated I/O Preset Clear Buffer

Truth Table

Function

PAD, IDE, CLK, IOPCL Q

FamilyModules

Seq I/O

ACT 3 1

Input Output

Input Register, with Clear, Input Data Enable

Truth Table

IOPCL IDE CLK Qn+1

0 X X 0

1 1 X Q

1 0 ↑ PAD

Function

PRECLK

PAD, IDE, CLK, IOPCL Q

FamilyModules

Seq I/O

ACT 3 1

Input Output

Input Register, with Preset, Input Data Enable

Truth Table

IOPCL IDE CLK Qn+1

0 X X 1

1 1 X Q

1 0 ↑ PAD

Function

OBUFTH

HIGH SLEW

D, E PAD

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Buffer, Tristate Enable, High Slew

Truth Table

D E PAD

Function

OBUFTL

LOW SLEW

D, E PAD

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Buffer, Tristate Enable, Low Slew

Truth Table

D E PAD

Function

ORECTH

HIGH SLEW

D, ODE, CLK, IOPCL, E PAD

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Register, with Clear, Output Data Enable, Tristate Enable, High Slew

Truth Table

IOPCL E ODE CLK PAD

0 1 X X 0

X 0 X X Z

1 1 0 ↑ D

Function

ORECTL

LOW SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Register, with Clear, Output Data Enable, Tristate Enable, Low Slew

Truth Table

IOPCL E ODE CLK PAD

0 1 X X 0

X 0 X X Z

1 1 0 ↑ D

Function

OREPTH

HIGH SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Register, with Preset, Output Data Enable, Tristate Enable, High Slew

Truth Table

IOPCL E ODE CLK PAD

0 1 X X 1

X 0 X X Z

1 1 0 ↑ D

Function

OREPTL

LOW SLEW

FamilyModules

Seq I/O

ACT 3 1

Input Output

Output Register, with Preset, Output Data Enable, Tristate Enable, Low Slew

Truth Table

IOPCL E ODE CLK PAD

0 1 X X 1

X 0 X X Z

1 1 0 ↑ D

Function

Axcelerator Input IO MacrosNames for the input buffers are composed of up to 4 parts:• A base name indicating the type of buffer :INBUF• IO Technology like LVCMOS• An optional number code 33,25,18 or 15 indicating a 3.3, 2.5, 1.8 OR 1.5 voltage level.• An optional one character code (U/D) designating a pull-up/down resistor. When the buffer has no

resistor, this code is omitted.For Example:• INBUF_LVCMOS25U - An input LVCMOS buffer with 2.5 CMOS voltage levels, pull-up resistor.• INBUF_PCIX - An input PCIX buffer

AxceleratorINBUF_X

FunctionGlobal Input Buffer

InputPAD

OutputY

Truth Table

Family

FamilyModules

Seq I/O

All listed 1

Available INBUF_X Macro Types

Name DescriptionINBUF LVTTL Input buffer with 3.3v voltage levelINBUF_LVCMOS25 LVCMOS Input buffer with 2.5 CMOS voltage levelINBUF_LVCMOS25U LVCMOS Input buffer with 2.5 CMOS voltage level, pull-up resistorINBUF_LVCMOS25D LVCMOS Input buffer with 2.5 CMOS voltage level, pull-down resistorINBUF_LVCMOS18 LVCMOS Input buffer with 1.8 CMOS voltage levelINBUF_LVCMOS18U LVCMOS Input buffer with 1.8 CMOS voltage level, pull-up resistorINBUF_LVCMOS18D LVCMOS Input buffer with 1.8 CMOS voltage level, pull-down resistorINBUF_LVCMOS15 LVCMOS Input buffer with 1.5 CMOS voltage levelINBUF_LVCMOS15U LVCMOS Input buffer with 1.5 CMOS voltage level, pull-up resistorINBUF_LVCMOS15D LVCMOS Input buffer with 1.5 CMOS voltage level, pull-down resistorINBUF_PCI PCI Input bufferINBUF_PCIX PCIX Input bufferINBUF_GTLP25 GTLP Input buffer with 3.3 CMOS voltage levelINBUF_GTLP33 GTLP Input buffer with 2.5 CMOS voltage levelINBUF_ HSTL _I HSTL Class I Input bufferINBUF_SSTL2_I SSTL2 Class I Input bufferINBUF_SSTL2_II SSTL2 Class II Input bufferINBUF_SSTL3_I SSTL3 Class I Input bufferINBUF_SSTL3_II SSTL3 Class II Input buffer

Bi-Directional IO MacrosNames for the bi-directional buffers are composed of up to 4 parts:• A base name indicating the type of buffer :BIBUF• Optional IO Technology like LVCMOS• An optional number code 8,12,16,24 indicating 1x, 2x, 3x or 4x-drive strength.• An optional one character code (S/F) indicating high(F) slew or low(S) slew• An optional one character code (U/D) designating a pull-up/down resistor. When the buffer has no

resistor, this code is omitted.For Example:• BIBUF_LVCMOS25 - A bi-directional LVCMOS buffer with 2.5 CMOS voltage levels, pull-up resis-

tor • BIBUF_S_8- A bi-directional buffer with low slew and 1x drive strength

Available BIBUF_X Macro Types

Name DescriptionBIBUF_LVCMOS25 LVCMOS Bi-directional buffer with 2.5 CMOS voltage levelBIBUF_LVCMOS25U LVCMOS Bi-directional buffer with 2.5 CMOS voltage level, pull-up resistorBIBUF_LVCMOS25D LVCMOS Bi-directional buffer with 2.5 CMOS voltage level, pull-down resistorBIBUF_LVCMOS18 LVCMOS Bi-directional buffer with 1.8 CMOS voltage levelBIBUF_LVCMOS18U LVCMOS Bi-directional buffer with 1.8 CMOS voltage level, pull-up resistorBIBUF_LVCMOS18D LVCMOS Bi-directional buffer with 1.8 CMOS voltage level, pull-down resistorBIBUF_LVCMOS15 LVCMOS Bi-directional buffer with 1.5 CMOS voltage levelBIBUF_LVCMOS15U LVCMOS Bi-directional buffer with 1.5 CMOS voltage level, pull-up resistorBIBUF_LVCMOS15D LVCMOS Bi-directional buffer with 1.5 CMOS voltage level, pull-down resistorBIBUF_PCI PCI Bi-directional bufferBIBUF_PCIX PCIX Bi-directional bufferBIBUF_GTLP25 GTLP Bi-directional buffer with 2.5 CMOS voltage levelBIBUF_GTLP33 GTLP Bi-directional buffer with 3.3 CMOS voltage levelBIBUF_F_8 Bi-directional buffer with high slew and 1x drive strengthBIBUF_F_8U Bi-directional buffer with high slew and 1x drive strength, pull-up resistorBIBUF_F_8U Bi-directional buffer with high slew and 1x drive strength, pull-down resistorBIBUF_F_12 Bi-directional buffer with high slew and 2x drive strengthBIBUF_F_12U Bi-directional buffer with high slew and 2x drive strength, pull-up resistorBIBUF_F_12D Bi-directional buffer with high slew and 2x drive strength, pull-down resistorBIBUF_F_16 Bi-directional buffer with high slew and 3x drive strengthBIBUF_F_16U Bi-directional buffer with high slew and 3x drive strength, pull-up resistorBIBUF_F_16D Bi-directional buffer with high slew and 3x drive strength, pull-down resistorBIBUF_F_24 Bi-directional buffer with high slew and 4x drive strengthBIBUF_F_24U Bi-directional buffer with high slew and 4x drive strength, pull-up resistorBIBUF_F_24D Bi-directional buffer with high slew and 4x drive strength, pull-down resistorBIBUF_S_8 Bi-directional buffer with low slew and 1x drive strengthBIBUF_S_8U Bi-directional buffer with low slew and 1x drive strength, pull-up resistorBIBUF_S_8U Bi-directional buffer with low slew and 1x drive strength, pull-down resistorBIBUF_S_12 Bi-directional buffer with low slew and 2x drive strengthBIBUF_S_12U Bi-directional buffer with low slew and 2x drive strength, pull-up resistorBIBUF_S_12D Bi-directional buffer with low slew and 2x drive strength, pull-down resistorBIBUF_S_16 Bi-directional buffer with low slew and 3x drive strengthBIBUF_S_16U Bi-directional buffer with low slew and 3x drive strength, pull-up resistorBIBUF_S_16D Bi-directional buffer with low slew and 3x drive strength, pull-down resistorBIBUF_S_24 Bi-directional buffer with low slew and 4x drive strengthBIBUF_S_24U Bi-directional buffer with low slew and 4x drive strength, pull-up resistorBIBUF_S_24D Bi-directional buffer with low slew and 4x drive strength, pull-down resistor

AxceleratorBIBUF_X

D PADE

FunctionBidirectional Buffer, High Slew (with Hidden Buffer at Y pin)

InputD, E, PAD

OutputY, PAD

Truth Table

Family

MODE E D PAD Y

OUTPUT 1 X D D

INPUT 0 X X PAD

FamilyModules

Seq I/O

BIBUF_SSTL2_I SSTL2 Class I Bi-directional buffer with 2.5V CMOS Voltage LevelBIBUF_SSTL2_II SSTL2 Class II Bi-directional buffer with 2.5V CMOS Voltage LevelBIBUF_SSTL3_I SSTL3 Class I Bi-directional buffer with 3.3V CMOS Voltage LevelBIBUF_SSTL3_II SSTL3 Class II Bi-directional buffer with 3.3V CMOS Voltage LevelBIBUF_HSTL_I HSTL Class I Bi-directional buffer with 1.5V CMOS Voltage Level

Name Description

Clock Buffers Names for the input buffers are composed of up to 3 parts:• A base name indicating the type of buffer :CLKBUF• IO Technology like LVCMOS• An optional number code 33,25,18 or 15 indicating a 3.3,2.5, 1.8 OR 1.5 voltage level

AxceleratorCLKBUF_X

FunctionInput for Dedicated Routed Clock Network

InputPAD

OutputY

Truth Table

Family

NOTE 2: Refer to Actel’s Databook for more Clock Network informa-tion.

FamilyModules

Seq I/O

Available CLKBUF_X Macro Types

Name DescriptionCLKBUF_LVCMOS25 LVCMOS Clock buffer with 2.5 CMOS voltage levelCLKBUF_LVCMOS18 LVCMOS Clock buffer with 1.8 CMOS voltage levelCLKBUF_LVCMOS15 LVCMOS Clock buffer with 1.5 CMOS voltage levelCLKBUF_PCI PCI Clock bufferCLKBUF_PCIX PCIX Clock bufferCLKBUF_GTLP25 GTLP Clock buffer with 2.5 CMOS voltage levelCLKBUF_GTLP33 GTLP Clock buffer with 3.3 CMOS voltage levelCLKBUF_ HSTL _I HSTL Class I Clock bufferCLKBUF_SSTL2_I SSTL2 Class I Clock bufferCLKBUF_SSTL2_II SSTL2 Class II Clock bufferCLKBUF_SSTL3_I SSTL3 Class I Clock bufferCLKBUF_SSTL3_II SSTL3 Class II Clock buffer

HClock BuffersNaming convention is identical to the naming for Clock Buffers.

AxceleratorHCLKBUF_X

FunctionDedicated high-speed S-Module Clock Buffer

InputPAD

OutputY

Truth Table

Family

NOTE 1: Refer to Actel’s Databook for more Clock Network informa-tion.

FamilyModules

Seq I/O

Available HCLKBUF_X Macro Types

Name DescriptionHCLKBUF_LVCMOS25 LVCMOS Clock buffer with 2.5 CMOS voltage levelHCLKBUF_LVCMOS18 LVCMOS Clock buffer with 1.8 CMOS voltage levelHCLKBUF_LVCMOS15 LVCMOS Clock buffer with 1.5 CMOS voltage levelHCLKBUF_PCI PCI Clock bufferHCLKBUF_PCIX PCIX Clock bufferHCLKBUF_GTLP25 GTLP Clock buffer with 2.5 CMOS voltage levelHCLKBUF_GTLP33 GTLP Clock buffer with 3.3 CMOS voltage levelHCLKBUF_ HSTL _I HSTL Class I Clock bufferHCLKBUF_SSTL2_I SSTL2 Class I Clock bufferHCLKBUF_SSTL2_II SSTL2 Class II Clock bufferHCLKBUF_SSTL3_I SSTL3 Class I Clock bufferHCLKBUF_SSTL3_II SSTL3 Class II Clock buffer

Output BuffersNames for the bi-directional buffers are composed of up to 4 parts:• A base name indicating the type of buffer :OUTBUF• Optional IO Technology like LVCMOS• An optional number code 8,12,16,24 indicating 1x, 2x, 3x or 4x-drive strength.• An optional one character code (S/F) indicating high(F) slew or low(S) slew

AxceleratorOUTBUF_X

FunctionOutput Buffer, High Slew

InputD

OutputPAD

Truth Table

Family

FamilyModules

Seq I/O

Available OUTBUF_X Macro Types

Name DescriptionOUTBUF_LVCMOS25 LVCMOS Output buffer with 2.5 CMOS voltage levelOUTBUF_LVCMOS18 LVCMOS Output buffer with 1.8 CMOS voltage levelOUTBUF_LVCMOS15 LVCMOS Output buffer with 1.5 CMOS voltage levelOUTBUF_PCI PCI Output bufferOUTBUF_PCIX PCIX Output bufferOUTBUF_GTLP25 GTLP Output buffer with 2.5 CMOS voltage levelOUTBUF_GTLP33 GTLP Output buffer with 3.3 CMOS voltage levelOUTBUF_F_8 Output buffer with high slew and 1x drive strengthOUTBUF_F_12 Output buffer with high slew and 2x drive strengthOUTBUF_F_16 Output buffer with high slew and 3x drive strengthOUTBUF_F_24 Output buffer with high slew and 4x drive strengthOUTBUF_S_8 Output buffer with low slew and 1x drive strengthOUTBUF_S_12 Output buffer with low slew and 2x drive strengthOUTBUF_S_16 Output buffer with low slew and 3x drive strengthOUTBUF_S_24 Output buffer with low slew and 4x drive strengthOUTBUF_SSTL2_I SSTL Class I Output buffer with 2.5V CMOS Voltage LevelOUTBUF_SSTL2_II SSTL Class II Output buffer with 2.5V CMOS VoltageOUTBUF_SSTL3_I SSTL Class I Output buffer with 3.3V CMOS Voltage LevelOUTBUF_SSTL3_II SSTL Class II Output buffer with 3.3V CMOS Voltage LevelOUTBUF_HSTL_I HSTL Class I Output buffer with 1.5V CMOS Voltage Level

Tri-State Buffer MacrosNames for the bi-directional buffers are composed of up to 4 parts:• A base name indicating the type of buffer :TRIBUFF• Optional IO Technology like LVCMOS• An optional number code 8,12,16,24 indicating 1x, 2x, 3x or 4x-drive strength.• An optional one character code (S/F) indicating high(F) slew or low(S) slew• An optional one character code (U/D) designating a pull-up/down resistor. When the buffer has no

resistor, this code is omitted.For Example:• TRIBUFF_LVCMOS25 - A bi-directional LVCMOS buffer with 2.5 CMOS voltage levels, pull-up

resistor • TRIBUFF_S_8- A bi-directional buffer with low slew and 1x drive strength

Available TRIBUFF_X Macro Types

Name DescriptionTRIBUFF_LVCMOS25 LVCMOS Tri-state buffer with 2.5 CMOS voltage levelTRIBUFF_LVCMOS25U LVCMOS Tri-state buffer with 2.5 CMOS voltage level, pull-up resistorTRIBUFF_LVCMOS25D LVCMOS Tri-state buffer with 2.5 CMOS voltage level, pull-down resistorTRIBUFF_LVCMOS18 LVCMOS Tri-state buffer with 1.8 CMOS voltage levelTRIBUFF_LVCMOS18U LVCMOS Tri-state buffer with 1.8 CMOS voltage level, pull-up resistorTRIBUFF_LVCMOS18D LVCMOS Tri-state buffer with 1.8 CMOS voltage level, pull-down resistorTRIBUFF_LVCMOS15 LVCMOS Tri-state buffer with 1.5 CMOS voltage levelTRIBUFF_LVCMOS15U LVCMOS Tri-state buffer with 1.5 CMOS voltage level, pull-up resistorTRIBUFF_LVCMOS15D LVCMOS Tri-state buffer with 1.5 CMOS voltage level, pull-down resistorTRIBUFF_PCI PCI Tri-state bufferTRIBUFF_PCIX PCIX Tri-state bufferTRIBUFF_GTLP25 GTLP Tri-state buffer with 2.5 CMOS voltage levelTRIBUFF_GTLP33 GTLP Tri-state buffer with 3.3 CMOS voltage levelTRIBUFF_F_8 Tri-state buffer with high slew and 8 mA drive strengthTRIBUFF_F_8U Tri-state buffer with high slew and 1x drive strength, pull-up resistorTRIBUFF_F_8U Tri-state buffer with high slew and 1x drive strength, pull-down resistorTRIBUFF_F_12 Tri-state buffer with high slew and 2x drive strengthTRIBUFF_F_12U Tri-state buffer with high slew and 2x drive strength, pull-up resistorTRIBUFF_F_12D Tri-state buffer with high slew and 2x drive strength, pull-down resistorTRIBUFF_F_16 Tri-state buffer with high slew and 3x drive strengthTRIBUFF_F_16U Tri-state buffer with high slew and 3x drive strength, pull-up resistorTRIBUFF_F_16D Tri-state buffer with high slew and 3x drive strength, pull-down resistorTRIBUFF_F_24 Tri-state buffer with high slew and 4x drive strengthTRIBUFF_F_24U Tri-state buffer with high slew and 4x drive strength, pull-up resistor

AxceleratorTRIBUFF_X

D PADE

FunctionTristate Output, High Slew

InputD, E

OutputPAD

Truth Table

Family

FamilyModules

Seq I/O

TRIBUFF_F_24D Tri-state buffer with high slew and 4x drive strength, pull-down resistorTRIBUFF_S_8 Tri-state buffer with low slew and 1x drive strengthTRIBUFF_S_8U Tri-state buffer with low slew and 1x drive strength, pull-up resistorTRIBUFF_S_8U Tri-state buffer with low slew and 1x drive strength, pull-down resistorTRIBUFF_S_12 Tri-state buffer with low slew and 2x drive strengthTRIBUFF_S_12U Tri-state buffer with low slew and 2x drive strength, pull-up resistorTRIBUFF_S_12D Tri-state buffer with low slew and 2x drive strength, pull-down resistorTRIBUFF_S_16 Tri-state buffer with low slew and 3x drive strengthTRIBUFF_S_16U Tri-state buffer with low slew and 3x drive strength, pull-up resistorTRIBUFF_S_16D Tri-state buffer with low slew and 3x drive strength, pull-down resistorTRIBUFF_S_24 Tri-state buffer with low slew and 4x drive strengthTRIBUFF_S_24U Tri-state buffer with low slew and 4x drive strength, pull-up resistorTRIBUFF_S_24D Tri-state buffer with low slew and 4x drive strength, pull-down resistorTRIBUFF_SSTL2_I SSTL2 Class I Tri-state buffer with 2.5V CMOS Voltage LevelTRIBUFF_SSTL2_II SSTL2 Class II Tri-state buffer with 2.5V CMOS Voltage LevelTRIBUFF_SSTL3_I SSTL3 Class I Tri-state buffer with 3.3V CMOS Voltage LevelTRIBUFF_SSTL3_II SSTL3 Class II Tri-state buffer with 3.3V CMOS Voltage LevelTRIBUFF_HSTL_I HSTL Class I Tri-state buffer with 1.5V CMOS Voltage Level

Name Description

Differential IO Macros

AxceleratorINBUF_LVDS; INBUF_LVPECL

FunctionINBUF_LVDS and INBUF_LVPECL

InputPADP; PADN

OutputY

Available Differential Macro Types

Name DescriptionINBUF_LVDSINBUF_LVPECL

AxceleratorCLKBUF_LVDS; CLKBUF_LVPECL

FunctionCLKBUF_LVDS and CLKBUF_LVPECL

InputPADP; PADN

OutputY

Name DescriptionCLKBUF_LVDSCLKBUF_LVPECL

AxceleratorHCLKBUF_LVDS; HCLKBUF_LVPECL

FunctionHCLKBUF_LVDS and HCLKBUF_LVPECL

InputPADP; PADN

OutputY

Name DescriptionHCLKBUF_LVDSHCLKBUF_LVPECL

AxceleratorOUTBUF_LVDS; OUTBUF_LVPECL

FunctionOUTBUF_LVDS and OUTBUF_LVPECL

InputD

OutputPADP, PADN

Name DescriptionOUTBUF_LVDSOUTBUF_LVPECL

DDR Macro

AxceleratorDDR_REG macro

FunctionDDR (DDR) Register with activelow write and rad enables; please refer to the

Axcelerator datasheet for more information on the DDR_REG

InputD, CLK, E, PRE, CLR

OutputQR, QF

Truth Table

CLR PRE E CLK QR(n+1) QF(n+1)

0 X X X 0 0

1 0 X X 1 1

1 1 1 X QR(n) QF(n)

1 1 0 ↑ D(↑) X

1 1 0 ↓ X D(↓)

Carry Chain Macros

A, B, FCI S, FCO

FamilyModules

All listed 1

Input Output

1 Bit Adder

Truth Table A B FCI S FCO

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Function

Axcelerator

A, B, FCI S, FCO

FamilyModules

All listed 1

Input Output

1 Bit Subtractor

Truth Table A B FCI S FCO

0 0 0 0 0

0 0 1 1 1

0 1 0 1 1

0 1 1 0 1

1 0 0 1 0

1 0 1 0 0

1 1 0 0 0

1 1 1 1 1

Function

Axcelerator

AxceleratorADDSUB1

Function1 Bit Add Sub macro

InputAS, B, A, FCI

OutputS, FCO

Truth Table

AS B A FCI S FCO

0 0 0 0 1 0

0 0 0 1 0 1

0 0 1 0 0 1

0 0 1 1 1 1

0 1 0 0 0 0

0 1 0 1 1 0

0 1 1 0 1 0

0 1 1 1 0 1

1 0 0 0 0 0

1 0 0 1 1 0

1 0 1 0 1 0

1 0 1 1 0 1

1 1 0 0 1 0

1 1 0 1 0 1

1 1 1 0 0 1

1 1 1 1 1 1

Family

FamilyModules

All listed 2

AxceleratorMULT1

Function1 Bit Multiplier

InputA, B, PI, FCI

OutputPO, FCO

Truth Table

A B PI FCI PO FCO

0 0 0 0 0 0

0 0 0 1 1 0

0 0 1 0 1 0

0 0 1 1 0 1

0 1 0 0 0 0

0 1 0 1 1 0

0 1 1 0 1 0

0 1 1 1 0 1

1 0 0 0 0 0

1 0 0 1 1 0

1 0 1 0 1 0

1 0 1 1 0 1

1 1 0 0 1 0

1 1 0 1 0 1

1 1 1 0 0 1

1 1 1 1 1 1

Family

FamilyModules

All listed 1

AxceleratorARCNTECP1Function1 Bit counter

InputFCI, CLK, PRE, CLR, UD

OutputQ, FCO

Truth Table

FCI UD PRE CLR E CLK FCO Qn+1

X X 0 X X X X 1

X X 1 0 X X X 0

X X 1 1 1 X X Qn

See Equations 1 1 0 ↑ See Equations

Qn 1+ FCI UD Qn∧ ∧=

FCO FCI.UD FCI.Qn UD.Qn+ +=

Family

FamilyModules

Comb Seq

All listed 1 1

AxceleratorAFCNTECP1

Function1 Bit counter

OutputQ, FCO

Truth Table

X X 0 X X X X 1

X X 1 0 X X X 0

X X 1 1 1 X X Qn

See Equations 1 1 0 ↓ See Equations

Family

FamilyModules

Comb Seq

All listed 1 1

AxceleratorSRCNTECP1

OutputQ, FCO

Truth Table

X X 0 X X X X 1

X X 1 0 X X X 0

X X 1 1 1 X X Qn

See Equations 1 1 0 ↑ See Equations

Qn 1+ FCI !UD Qn∧ ∧=

FCO FCI.!UD FCI.Qn !UD.Qn+ +=

Family

FamilyModules

Comb Seq

All listed 1 1

AxceleratorSFCNTECP1

OutputQ, FCO

Truth Table

X X 0 X X X X 1

X X 1 0 X X X 0

X X 1 1 1 X X Qn

See Equations 1 1 0 ↓ See Equations

Family

FamilyModules

Comb Seq

All listed 1 1

AxceleratorARCNTELDCP1

InputFCI, CLK, PRE, CLR, E, LD, D, and UD

Truth Table

FCI UD PRE CLR E LD D CLK FCO Qn+1

X X 0 X X X X X X 1

X X 1 0 X X X X X 0

X X 1 1 1 X X X X On

X X 1 1 0 1 0 ↑ X 0

X X 1 1 0 1 1 ↑ X 1

See Equations 1 1 0 0 X ↑ See

Equations

Family

FamilyModules

Comb Seq

All listed 2 1

OutputQ, FCO

AxceleratorAFCNTELDCP1

Truth Table

X X 0 X X X X X X 1

X X 1 0 X X X X X 0

X X 1 1 1 X X X X Qn

X X 1 1 0 1 0 ↓ X 0

X X 1 1 0 1 1 ↓ X 1

See Equations 1 1 0 0 X ↓ See

Equations

FCO FCI.UD FCI.Qn UD.Qn+ +=Family

FamilyModules

Comb Seq

All listed 2 1

OutputQ, FCO

AxceleratorSRCNTELDCP1

Truth Table

X X 0 X X X X X X 1

X X 1 0 X X X X X 0

X X 1 1 0 1 0 ↑ X 0

X X 1 1 0 1 1 ↑ X 1

See Equations 1 1 0 0 X ↑ See

Equations

Family

FamilyModules

Comb Seq

All listed 2 1

OutputQ, FCO

AxceleratorSFCNTELDCP1

Truth Table

X X 0 X X X X X X 1

X X 1 0 X X X X X 0

X X 1 1 0 1 0 ↓ X 0

X X 1 1 0 1 1 ↓ X 1

See Equations 1 1 0 0 X ↓ See

Equations

Family

FamilyModules

Comb Seq

All listed 2 1

OutputQ, FCO

AxceleratorFCEND_BUFF

FunctionBuffer, driven by the FCO pin of the last macro in the Carry-Chain

InputA

OutputY

Truth Table

Family

FamilyModules

Seq COMB

AxceleratorFCEND_INV

FunctionInverter with Active Low output; driven by the FCO pin of the last macro in the

Carry-Chain

InputA

OutputY

Truth Table

Family

FamilyModules

Seq COMB

AxceleratorFCINIT_BUFF

FunctionBuffer, used to initialize the FCI pin of the first macro in the Carry-Chain with

an external signal

InputA

OutputY

Truth Table

Family

FamilyModules

Seq COMB

AxceleratorFCINIT_GND

FunctionGround; used to initialize the FCI pin of the first macro in the Carry-Chain to

Input OutputY

NOTE: Ground does not use any modules

AxceleratorFCINIT_INV

FunctionInverter with Active Low output; used to initialize the FCI pin of the first macro

in the Carry-Chain with an external signal

InputA

OutputY

Truth Table

Family

FamilyModules

Seq COMB

AxceleratorFCINIT_VCC

FunctionPower; used to initialize the FCI pin of the first macro in the Carry-Chain to

InputA

OutputY

NOTE: VCC does not use any modules

PLL Macros

AxceleratorPLL; PLLFB

DELAYLINE1DELAYLINE0

DIVJ5DIVJ4DIVJ3DIVJ2DIVJ1

DIVI5DIVI4DIVI3DIVI2DIVI1

PWRDWN

REFCLK

LOWFREQ

DELAYLINE2DELAYLINE3DELAYLINE4

FunctionPLL: PLL with internal feedback; PLLFB: PLL with external feedback. NOTE: PLL and PLLFB are identical except for the FB pin; if you wish to use

internal feedback, use the regular PLL.

InputPWRDWN, REFCLK, LOWFREQ, OSC2, OSC1, OSC0, DIVI5, DIVI4, DIVI3, DIVI2, DIVI1, DIVI0, DIVJ5, DIVJ4, DIVJ3, DIVJ2, DIVJ1, DIVJ0, DELAYLINE4, DELAYLINE3, DELAYLINE2, DELAYLINE1, DELAYLINE0

OutputLOCK, CLK1, CLK2

Actel recommends that you use ACTgen to generate your PLLs; ACTgen calcu-lates the settings for all the pins in the PLL for the required input-output fre-quency combinations.

Refer to the latest Actel datasheets on PLLs for Axcelerator for more information. They are available at http://www.actel.com.

AxceleratorPLLINT

FunctionPLL Int

InputA

OutputY

Truth Table

Connect only to the REFCLK input of PLL when the PLL is driven by a pad other than the one in the same super cluster.

AxceleratorPLLOUT

FunctionPLL OUT

InputA

OutputY

Truth Table

Connect only to the CLK output of PLL when the PLL is driving a net other than the HCLK/RCLK networks.

AxceleratorPLLHCLK

FunctionPLL HCLK

InputA

OutputY

Truth Table

Connect only to the CLK output of the PLL; use it to drive the HCLK network.

AxceleratorPLLRCLK

FunctionPLL RCLK

InputA

OutputY

Truth Table

Connect only to the CLK output of the PLL; use it to drive the RCLK network.

Antifuse Macro Library Guide

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