Analog Layout - Resistors

• dummy resistor should be added in order to minimize the faster etchingin large areas

•Contact resistance must be taken into account for small resistance values

•In order to minimize the noise, the resistor can be designed•with a guard ring •inside a well to reduce the coupling to the substrate

•matching between resistors requires that the resistors are designed in the layout :

• with the same orientation • distributed in a interdigitized or common centroid style

Analog Layout - Resistors

• dummy capacitors should be added in order to minimize the faster etching in large areas

• In order to minimize the noise, the capacitor can be designed•with a guard ring •inside a well to reduce the coupling to the substrate

•matching between capacitors requires that the capacitors are designed in the layout using a common centroid style

Analog Layout - Capacitors

• The gate resistance is reduced by dividing the gate in several sections (each section with a width < 40um). N transistors can be instantiated in parallel if the instance name is INST_NAME<1:N>

• The gate resistance is reduced also by adding contacts in both sides of the poly stripes that implement the gate

• dummy gates can be added in order to minimize the faster etching in large areas

•Guard rings are usefull to obtain noise imunity and good substrate biasing, preventing latch-up

•matching between transistors requires that the layout is designed:• using large areas for the gates• without metal overlapping the gates • distributed in a interdigitized or common centroid style

Analog Layout - Transistors

Analog Layout - Transistors

Analog Layout - Transistors

Common-Centroid Layout:Matching obtained by dividing the gates in two

Topology: DASBDBSAD

BA

Analog Layout - Matching

Analog Layout - Matching

Examples of interdigitized MOS topologies:

1. (DASBDBSA)D A:B = 1:1

2. (SADA)(SBDBSBDB)(SADAS)

3. (SADASBDB)S(BDBSADAS)

4. (SADASBDBSADA)S A:B = 2:1

5. (SADASBDBSCDC)S(CDCSBDBSADAS) A:B:C = 1:1:1

Analog Layout - Matching

Common-Centroid layout design guidelines:

1. Placement: The geometric center of the devices to match must be very near

2. Symmetry: The layout of the devices must be evenly distributed in bothdirections: x and y

3. Regularity: Partial devices must be distributes uniformly

4. Dispersion: The layout must be as compact and square as possible

5. Orientation: The number of partial devices oriented in each direction mustbe the same for each device to be match.

Analog Layout - Matching

DASBD

DBSAD

B A

• A B / B A compliant with the orientation guideline

Dividing each transistorin two transistors

Common-Centroid

Analog Layout - Matching

DASBDBSAD

DBSADASBD

Dividing each transistorin 4 transistors

Common-Centroid

Analog Layout - Matching

DASBDBSAD

DBSADASBD

DASBDBSAD

DBSADASBD

Common-Centroid

DASBDBSADASBDBSAD

DBSADASBDBSADASBD

DASBDBSADASBDBSAD

DBSADASBDBSADASBD

DASBDBSADASBDBSAD

DBSADASBDBSADASBD

Analog Layout - Matching

Common Source Stage : Voltage Gain

Common Drain Stage: Output Resistance

Common Gate Stage : Input Resistance

Single stage basic topologies summary

Single stage bandwidth comparison

2 stage ampopStabilized bias circuit

Analog Layout – 2 stage AMPOP

Analog design

Initial design criteria (after reading process parameter data):

• current budget limited• overdrive voltage: VGS-VT > 200mV• Lmin = 1µm (avoid short channel effects

and limit sub-threshold current)• W.Lmin: Offset limited• W/L : gm limited

Overdrive in the differential the pair

> overdrive voltage ⇒ > linearity, < gm

Vos in the differential the pair

diffdiff

VTdiffTdiffOS LW

AVV 3_max__ =∆=

99,7%

24_ // oodiffmd rrgA =

diffToodiffmdiffO VrrgV _24__ // ∆×=

Vos in the differential the pair (c. mirror)

diffm

mirrm

mirrmirr

VTmirrOS g

gLW

AV_

_max__

3=

( ) ( )2_

2_ mirrOSdiffOSOS VVV +=

mirrToomirrmmirrO VrrgV _24__ // ∆×=

24_ // oodiffmd rrgA =

Gain between 5,000 and 10,000

• Advantage: higher gain• Inconvenient: highly restricted common mode

•Ro = Ro2C // Ro4C= (gm2C ro2C ro2)//(gm4C ro4C ro3)

•A1 = - gm1 Ro

Analog Layout – Cascode dif. pair

Folded-CascodeCascode versus

Analog Layout – Cascode dif. pair

Ro = Ro2C//Ro4C= [gm2C ro2C (ro7//ro2)]//(gm4C ro4C ro3)

A = gm1 Ro

Advantage: extended common mode

Analog Layout – Cascode dif. pair

Analog Layout – Folded cascode AMPOP

Enhanced current mirror

VBE + Self-biasing Circuit

Analog Layout – Bandgap example