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Prof Jess Role @UEAB 2008
ANALOG - DIGITAL
CONVERTERSLecture 10
Prof Jess Role @UEAB 2008
Analog to Digital Conversion Introduction
The sampling problem
Conversion errors
Different types of A-to-D converters
Applications
Prof Jess Role @UEAB 2008
WHY TO GO TO DIGITAL WORDS ?
Benefits of Computer Power for further signal processing
Permanent Data Storage
Introduction to Analog to Digital Conversion
Prof Jess Role @UEAB 2008
Prof Jess Role @UEAB 2008
Prof Jess Role @UEAB 2008
INTERFACE BETWEEN “ANALOGUE” SIGNALS AND DIGITAL (BINARY) REPRESENTATIONS
TWO ALTERATIONS OF THE SIGNAL: Signal is sampled at given instants (sampling time) Continuous amplitude is encoded to a limited number of binary
word, i.e. a binary word represents an interval of amplitude (quantization)
Introduction to Analog to Digital Conversion
Time
Binary code
0000100010
000110010000101
…..
Prof Jess Role @UEAB 2008
RESTITUTION OF THE SIGNAL THROUGH A DAC (Digital-to-Analogue Converter)
DIGITIZATION IS A CRUCIAL SIGNAL TRANSFORM and both transformations aspects (Time Sampling and Amplitude Quantization) have to be considered
Introduction to Analog to Digital Conversion
Time
Binary code
0000100010
000110010000101
…..
Prof Jess Role @UEAB 2008
Relationship between quantization error, number of bits, resolution:
Introduction to Analog to Digital Conversion
Binary code
00001
00010
00011
00100
00101
…..
Amplitude interval : LSB=A/2n
Ex : 8 bits ADC, 1V Full Scale AmplitudeResolution (LSB) = 1/28 = 3.9 mV (0.39%)
A = maximum amplitude
n = number of bits
Max Quantization error : Q = +/- LSB/2 (ideal)
Quantization noise : 12LSB
Prof Jess Role @UEAB 2008
Introduction to Analog to Digital Conversion
Dynamic Range Ratio between the minimum and the maximum amplitude to be
measured
In case of a linear ADC, the dynamic range is related to the number of bits (and hence the resolution) an 8-bit ADC has a dynamic range of 256
In case of large dynamic range (as for calorimeter signals in HEP) the dynamic range could be as high as 2 106 : a linear ADC would require 21 bits! Some non-linearity is then introduced and there is distinction between
dynamic range and resolution n-bit resolution N-bit dynamic range (N>n) example:
12-bit resolution for a 16-bit dynamic range means that a signal in the range 1-65000 is measured with a resolution of 0.02%
Prof Jess Role @UEAB 2008
The perfect ADC would be the one with a very high number of quantization levels (high resolution) and at the same time very high sampling rate
Unfortunately this is not possible : different ADC architectures are existing, each one is offering a different compromise between resolution and sampling rate
Introduction to Analog to Digital Conversion
Prof Jess Role @UEAB 2008
Introduction to Analog to Digital Conversion
There is a trade-off between sampling rate and number of bits The choice of an ADC architecture is driven by the application
Speed (sampling rate)
Number of bits
Flash
Sub-Ranging
Pipeline
Successive Approximation
RampSigma-Delta
GHz
Hz
6 18
bipolar
CMOS
Discrete
Power
>W
<mW
Prof Jess Role @UEAB 2008
The sampling problem The sampling problem
If sampling is done with rate of 1 Hertz (green points), blue and red curves can not be distinguished
To represent the 1 Hertz blue signal, at least two samples per period are needed (on picture, the additional purple point), i.e. sampling at 2 Hertz
Sampling Frequency =1HzSampling Frequency =2Hz
1 Hz signal
2 Hz signal
Prof Jess Role @UEAB 2008
The sampling problem The sampling problem interpretations:
To represent a signal with maximum frequency f0, it is needed to sample at minimum frequency 2*f0 (Shannon Theorem)
Sampling at frequency fs is applicable to signals with bandwidth limited to fs/2
Fs/2 Fs
“analogue” signal spectrum
For conversion with an ADC sampling at frequency fs (Nyquist Rate ADC), the signal frequency bandwidth HAS TO BE LIMITED to fs/2
Prof Jess Role @UEAB 2008
The sampling problem Frequency representation of sampled signals
Fs/2 Fs
Fs/2 Fs 2Fs
“analogue” signal spectrum
“sampled” signal spectrum
Fs/2 Fs 2Fs
“sampled” signal spectrum with first order “hold”
Prof Jess Role @UEAB 2008
ADC errors : transfer curve
Ideal ADC Errors
Offset Integral non-linearity Differential non-linearity Missing code or non-monotonicity
-2
0
2
4
6
8
10
12
0 2 4 6 8 10 12
Vin
AD
C c
ou
nt
Prof Jess Role @UEAB 2008
ADC errors : Integral Non Linearity (INL)
Non linearity: maximum difference between the best linear fit and the ideal curve
0
2
4
6
8
10
12
0 5 10 15
Vin
ADC
coun
t Vout
Ideal
Linear (Vout)
Non Linearity
0
20
40
60
80
100
120
0 20 40 60 80 100 120
Prof Jess Role @UEAB 2008
ADC errors : Differential Non-Linearity (DNL)
Least Significant Bit (LSB) value should be constant but it is not
The difference with the ideal value shall not exceed 0.5 LSB Easy way of seeing the effect
random input covering the full range frequency histogram should be flat differential non-linearity introduces structures
ADCbitn2
V LSB 1
n
max
Analog Input
Code
+0.5LSB DNL
-0.6LSB DNL
Prof Jess Role @UEAB 2008
ADC errors : Missing code, monotonicity
Other conversion errors : non-monotonic ADC Missing code
Missing code
Non-monotonic
Prof Jess Role @UEAB 2008
ADC errors : Effective number of bits (ENB)
Measurement of the SNR indicates the Effective number of bits ENB
Example: AD9235 12-bit 20 to 65 MHz SNR (measured) = 70 dB Effective number of bits = 11.4
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3 3.5
(x)q
dxxq
1
2
q
2
q
2
q
2
q22
12
q An n bit ADC introduces a quantization
error
Encoding a signal (A/2) sint with A being the full scale will give an error
n
Aq2
222
2*1212
dBnSNR 8.16
Ideal Signal to Noise Ratio
Prof Jess Role @UEAB 2008
Types of ADC
Flash ADC & Subranging Flash ADC Pipeline ADC Successive Approximation ADC Ramp ADC Sigma-Delta
Prof Jess Role @UEAB 2008
Flash ADC Signal amplitude is compared to the
set of 2n references Direct “thermometric”
measurement with 2n-1 comparators
Typical performance: 4 to 10 bits (12 bits rare) Up to GHz (extreme case) High power (2n comparators) typ. 2W
Sampling
Prof Jess Role @UEAB 2008
Sub-ranging Flash ADC
Typical performance: 4 to 10 bits Up to 100 MHz Less power, but difficult analogue
functions (sample and hold, subtraction, DAC)
Half-Flash ADC– 2-step Flash ADC technique
» 1st flash conversion with 1/2 the precision» Residue calculation (1st flash conversion result reconstructed
with a DAC and subtracted from signal)» Residue flash conversion
4-bits + 4-bits sub-ranging flash needs 30 comparators(instead of 255 for 8-bits flash)
Required
Prof Jess Role @UEAB 2008
Pipeline ADC
Pipeline ADC Input-to-output delay = n clocks for n stages One output every clock cycle (as for Flash) Saves power (N comparators) Typ. 12 bits 40MHz 200mW
S&H
Comparator 1-bit DAC
-X 2
1-bit
S&H Stage 1 Stage 2 Stage 3 Stage N
Time Adjustment & Digital Error Correction
1-bit 1-bit 1-bit 1-bit
N-bit
Input
…………
Sampling
Prof Jess Role @UEAB 2008
Successive approximation Compare the signal with an n-bit
DAC output Change the code until
DAC output = ADC input
An n-bit conversion requires n steps
Requires a Start and an End signals
Typical conversion time– 1 to 50 s
Typical resolution– 8 to 12 bits
One comparator Power
– 10 mW
S&H
Sampling
Input
Prof Jess Role @UEAB 2008
Ramp ADC Start to charge a capacitor at
constant current Count clock ticks during this time Stop when the capacitor voltage
reaches the input Very slow, can reach very high
resolution (1s, 18 bits) with some further tricks (dual slope conversion)
-
+IN
C
R
S Enable
N-bit Output
Q
Oscillator Clk
Co
un
ter
StartConversion
StartConversion
02468
101214161820
0 2 4 6 8 10 12 14 16
Time
Vo
lta
ge
acc
ross
th
e c
ap
aci
tor
Vin
Counting time
(What’s used in digital multimeter)
S&HInput
Prof Jess Role @UEAB 2008
Over-sampling ADC
If fs/2 is higher than the maximum frequency f0 of the signal, then after filtering the quantization noise left in the signal frequency band (<f0) is :
0
0.5
1
1.5
2
2.5
3
3.5
0 0.5 1 1.5 2 2.5 3 3.5
(x)q
12
qdxx
q
1
2
q
2
q
2
2
q
2
q22
bitsofnumberthenandscalefullthebeingAwithf
fA
f
f
sn
s
00 2
12
1
2
2
Assuming the error is a white noise, its power spectral density is flat within the range [–fs/2,fs/2]
-fs/2 +fs/2f
|(f)|
sf
1
12
q
fs/2fs/2
Prof Jess Role @UEAB 2008
Over-sampling ADC (cont)
Hence it is possible to increase the resolution by increasing the sampling frequency and doing the proper filtering
Example :an 8-bit ADC would become a 12-bit ADC with an over-
sampling factor of 250 (!) But it is not an effective mean of increasing the resolution, because
the 8-bit ADC must meet the linearity requirements of a 12-bit ADC
The signal to noise ratio when encoding a signal with maximum frequency f0 with sampling at fs
bitsofnumbereffectivethebeingnnSNR
dBf
fnSNR s
''68.1
2log1068.1
0
Prof Jess Role @UEAB 2008
Sigma-Delta ADC
Over-sampling ADC using a feedback loop to further reduce noise in the low-frequency range have been developed : the most common today is the Sigma-Delta Converter
The feedback loop provides a further “noise shape” with effective noise reduction in the signal frequency band
1-bit ADC
1-bit DAC
-Input Output
1rst Order Sigma-Delta Modulator
Prof Jess Role @UEAB 2008
Sigma-Delta ADC
This architecture is highly tolerant to components imperfections
With strong Noise shaping and high linearity capability, Sigma-Delta modulators are capable of very high resolution (up to 22 bits)
However some other limitations may appear and several complex architectures are derived from the “basic” schema
1-bit ADC
1-bit DAC
-Input Output
1rst Order Sigma-Delta Modulator
Prof Jess Role @UEAB 2008
Sigma-Delta ADC
The output of this modulator is a digital stream, whose average value is an approximation of the input signal.
Quantization error in case of a first-order converter:
1-bit ADC
1-bit DAC
-Input Output
1rst Order Sigma-Delta Modulator
36 OSR
A (Over-sampling ratio OSR=fs/2f0)
Prof Jess Role @UEAB 2008
Sigma-Delta ADC (cont)
Gain of 1.5 bits per each doubling of M– M = 2400 to have a 16-bit ADC
Higher orders sigma-delta are implemented to reduce OSR
Examples (Analog Devices)– 16-bit, 2.5 MHz– 24-bit, 1kHz
The signal to noise ratio when encoding a signal (A/2) sint, with A being the full scale, will be
bitsofnumbereffectivethebeingnnSNR
dBMM
OSR
A
Ax
SNR
''68.1
4.3log308
36log10
36
8log10log102
3
3
22
2
2
2
Prof Jess Role @UEAB 2008
Applications In HEP we are facing large number of channels The quantity to be measured depends on the type of
detector Charge in the case of a lead glass calorimeter with PM read-out Voltage in the case of a lead glass calorimeter with triode and preamplifier shaper read-out
We are facing fast signals (mean frequency ~ 12 MHz) We are facing large dynamic range for calorimeter
signals (up to 16 bits)
Flash ADC are commonly used, but it is a high power device, and there
is no way to have one FADC per detector channel Calorimeters signals are too fast for using techniques
Prof Jess Role @UEAB 2008
FADC for LHC trigger purpose (1) Analog summation on the detector to
form the trigger tower Shaping time covers several bunch
crossings FADC and numerical filtering to:
Extract the energy Extract the bunch crossing responsible for it
Prof Jess Role @UEAB 2008
FADC for LHC trigger purpose (2)
Block diagram
Prof Jess Role @UEAB 2008
ADC for an LHC calorimeter (1) ATLAS Liquid Argon calorimeter High dynamic range: 16-bit Shaping of the signal to minimize pile-
up Sampling every 25 ns (bunch crossing
period) Level-1 pipeline
Shaping
Prof Jess Role @UEAB 2008
ADC for an LHC experiment (2)
Block diagram
Prof Jess Role @UEAB 2008
ADC for an LHC experiment (3)
Performance Pedestal stability to 0.1 ADC counts Noise equivalent to 20 MeV Integral non-linearity below 0.25% Conversion time : 25 ns per sample
Prof Jess Role @UEAB 2008
Resolution/Throughput Rate <10kHz 10 – 100 kHz 0.1 – 1 MHz 1 – 10 MHz 10 – 100 MHz > 100 MHz
>17 bits
14 – 16 bits
12 – 13 bits
10 – 11 bits
8 – 9 bits
<8 bits
Prof Jess Role @UEAB 2008
Digital Basics Digital to Analog Converter
Takes a digital input and converts it to an analog voltage output.
Digital Input: 0 – 255Analog Output: 0 – 2.55VResolution: ?? mV
Prof Jess Role @UEAB 2008
Digital Basics Digital to Analog Converter
Takes a digital input and converts it to an analog voltage output.
Digital Input: 0 – 255Analog Output: 0 – 2.55VResolution: 10 mV
Prof Jess Role @UEAB 2008
Digital Basics Types of Digital to Analog
Converters (DACs) Current Summing DAC R/2R Ladder DAC Integrated Circuit DAC
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
All switches at GND
IRF = IS2 + IS1 + IS0
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
All switches at GND
IRF = IS2 + IS1 + IS0
IRF = 0 A + 0 A + 0 A = 0A
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
All switches at GND
IRF = 0 A so VOUT = ?
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
All switches at GND
IRF = 0 A so VOUT = 0 V
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
S2 at +2V, S1 & S0 at GND
IRF = IS2 + IS1 + IS0
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
S2 at +2V, S1 & S0 at GND
IRF = IS2 + IS1 + IS0
IRF = 2 mA + 0 A + 0 A = 2 mA
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
S2 at +2V, S1 & S0 at GND
IRF = 2 mA so VOUT = ?
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
S2 at +2V, S1 & S0 at GND
IRF = 2 mA so VOUT = -2.0V
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
S2, S1 & S0 at +2V
IRF = IS2 + IS1 + IS0
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
S2, S1 & S0 at +2V
IRF = IS2 + IS1 + IS0
IRF = 2 mA + 1 mA + 0.5 mA = 3.5 mA
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
S2, S1 & S0 at +2V
IRF = 3.5 mA so VOUT = ?
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
S2, S1 & S0 at +2V
IRF = 3.5 mA so VOUT = -3.5V
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
S2 S1 S0 Expected VOUT
0 0 0 - 0.0 V0 0 1 - 0.5 V0 1 0 - 1.0 V0 1 1 - 1.5 V
Prof Jess Role @UEAB 2008
Current Summing DAC
4
6
7
3
2
R1
R2AR2B
R4AR4BR4CR4D
1KΩ
1KΩ1KΩ
1KΩ1KΩ1KΩ1KΩ
VOUT
+2 V
+12 V
-12 V
1KΩ
RF
S0
S1
S2
+
-
S2 S1 S0 Expected VOUT
1 0 0 - 2.0 V1 0 1 - 2.5 V1 1 0 - 3.0 V1 1 1 - 3.5 V
Prof Jess Role @UEAB 2008
TTL 74 Series Logic Chips Logic Level voltage ranges
VIN High = 2.0Vmin VIN Low = 0.8Vmax VOUT High = 2.4Vmin VOUT Low = 0.4V max
Indeterminate voltagesAny voltage between 0.8V and 2.0V on an inputcan not be guaranteed to be either high or low
Current capabilities IIN High = 40uA IIN Low = -1.6mA IOUT High = -0.4mA IOUT Low = 16mA
Prof Jess Role @UEAB 2008
TTL 74 Series Logic Chips
Fan outFan out (HIGH) = IOH(max) / IIH(max)
For 7400:400uA/40uA = 10Fan out (LOW) = IOL(max) / IIL(max)
For 7400:16mA/1.6mA = 10Propagations delays
How long does it take the output to change after a change has happened at the inputs
Prof Jess Role @UEAB 2008
Data Sheets
Floating inputs What happens if you don’t connect an input
to a high or low
CMOS family MOSFET switches instead of bipolar junction
transistor switches Faster than most standard TTL chips More susceptible to static electricity
Prof Jess Role @UEAB 2008
References
“Analog Integrated Circuit Design” David A. Johns, Ken Martin Wiley Publisher
“Analog MOS Integrated Circuits, I and II” Paul R. Gray, Bruce A. Wooley, Robert B. Brodersen, IEEE Press Books
About ADC, Sample and Hold
About Signal Sampling
“Digital Signal Processing”, Allan V. Oppenheim, Ronald W. Shaffer,
Prentice Hall Int. Publications
“Theory and Application of Digital Signal Processing” Lawrence R. Rabiner, Bernard Gold, Prentice Hall Int. Publications