Post on 19-Dec-2015
An Efficient Test Relaxation Technique for Synchronous
Sequential Circuits
Aiman El-Maleh and Khaled Al-UtaibiKing Fahd University of Petroleum & Minerals
Dhahran, Saudi Arabia
{aimane, alutaibi}@ccse.kfupm.edu.sa
2
Outline
Motivation Problem Definition & Test Relaxation Techniques Proposed Technique Selection Criteria Experimental Results Conclusions
3
Motivation
With today’s technology, complete systems with millions of transistors are built on a single chip.
Increasing complexity of systems-on-a-chip and its test data size increased cost of testing.
Cost of automatic test equipment increases with increase in speed, channel capacity, and memory.
Need for test data reduction is imperative• Test compaction
• Test compression
4
Motivation
Test compression and compaction techniques significantly improved based on a relaxed test.
Compression techniques:• LFSR-Reseeding require the test vectors to be partially
specified [Koenemann, ETS 91] [Hellebrand, ITS 92]
• Run-length coding benefits from partially specified test sets by specifying don't care values in a way that reduces number of runs [Jas, ITC 98] [Chandra, VTS 2000, VTS2001] [El-Maleh, VTS 2001, ICCD 2002]
Compaction:• In overlapping techniques, increasing the number of
X's in a test set reduces conflicts when merging two test sequences [Roy,88]
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Problem Definition & Test Relaxation Techniques
Given a synchronous sequential circuit and a fully specified test set, generate a partially specified test set that maintains the same fault coverage as the fully specified one while maximizing the number of unspecified bits.
Dynamic ATPG Compaction Bitwise-Relaxation
• Test for every bit of the test set whether changing it to an X reduces the fault coverage or not.
• O(nm) fault simulation runs, where n is the width of one test vector, and m is the number of test vectors
Test Relaxation Techniques for Combinational circuits• [El-Maleh, VTS 2002][Kajihara, ICCAD 2001]
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Proposed Test Relaxation Technique: General Behavior
At every time frame, t, all logic values necessary to detect a newly detected fault marked required.
Required logic values are justified backwards towards primary inputs and/or memory-elements.
Any primary input not marked as required during the justification process is relaxed.
Required values on the memory-elements are justified when time frame, t-1, is processed.
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Proposed Test Relaxation Technique: Relaxation Process
Fault Simulation: For every test vector t in the given test set, • fault simulate the circuit under that test vector• store faults newly detected in the current time frame• store faults propagating to the next time frame
Backward Justification: Starting from the last time frame down to the first one, • for every fault, f, that could not be justified in the previous
time frame justify fault-free/faulty values necessary to propagate f
• for every fault f newly detected in the current frame justify fault-free/faulty values necessary to detect f
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G1
G2G4
A
B
G5G2
G4
A
B
G5
G1
G3G3
titi+1
Proposed Test Relaxation Technique: Example
00
11
xx
00 //11
xx
00 xx
00 //1111 //00
00
00
00
00 11 //00
Consider the circuit shown below under two test vectors: ti = 01 and ti+1 = 00.
Assume that the only newly detected fault is A/1
Consider the circuit shown below under two test vectors: ti = 01 and ti+1 = 00.
Assume that the only newly detected fault is A/1
A/1A/1
//11
9
G1
G2G4
A
B
G5G2
G4
A
B
G5
G1
G3G3
titi+1
Proposed Test Relaxation Technique: Example
00 //11
11 /1/1
xx /x/x
00 //11
xx /x/x
00 /0/0 xx /x/x00 //11
11 //00
00 //11
00 /0/0
00 /0/0
00 /0/0 11 //00
Justify fault-free/faulty values necessary to detect A/1 starting from ti+1
Justify fault-free/faulty values necessary to detect A/1 starting from ti+1
A/1A/1x / 0x / 0
x / 0x / 0 x / 0x / 0
x / xx / x
10
G1
G2G4
A
B
G5G2
G4
A
B
G5
G1
G3G3
titi+1
Proposed Test Relaxation Technique: Example
00 //11
11 /1/1
xx /x/x
00 //11
xx /x/x
00 /0/0 xx /x/x00 //11
11 //00
xx /x/x
xx /0/0
xx /0/0
xx /0/0 11 //00
Since G5 is a memory-element, its fault-free/fault value can not be justified in ti+1
Thus, the justification process will continue in ti
Since G5 is a memory-element, its fault-free/fault value can not be justified in ti+1
Thus, the justification process will continue in ti
x/1x/1
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Selection Criteria in Value Justification
When justifying a controlling value through the inputs of a given gate, there could be more than one choice.
Priority is given to inputs already marked required Otherwise, cost functions are used to guide the
selection. Cost functions give a relative measure on the
number of primary inputs required to justify a given value.
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Selection Criteria
Let g be an AND Gate with i inputs and F(g) fanout branches [El-Maleh, VTS 2002]
Regular Cost Functions
Fanout-based Cost Functions
Weighted-Sum Cost Functions
i
regreg iCgC )()( 11 regi
reg iCgC )(min)( 00
)(
)(min)(
0
0gF
iCgC
fani
fan )(
)()(
1
1gF
iCgC i
fan
fan
)(.)(.)(
)(.)(.)(
111
000
ggg
ggg
CBCAC
CBCAC
fanreg
fanreg
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Selection Criteria: Example
Creg0(A) = 1
Creg0(B) = 1
Creg0(C) = 1
0
0G3
G1
G2
0
0
0
0
A
B
C
Cfan0(A) = 1
Cfan0(B) = 0.5
Cfan0(C) = 1
0
0G3
G1
G2
0
0
0
0
A
B
C
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Selection Criteria: Sequential Circuits
Controllability values in one time frame depend on values in the current and previous frames.
Controllability values computed in an iterative manner starting from the first time frame.
Iterative computation of controllability over several time frames may cause regular cost function to grow much faster than fanout-based cost function.
Effect of the second cost function in the weighted sum may become negligible.
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Selection Criteria: Sequential Circuits
G4
G1
G2
G3
1
1
1
1
1
1
Time Frame 1
G4
G1
G2
G3
1
1
1
1
1
1
Time Frame 2
G4
G1
G2
G3
1
1
1
1
1
1
Time Frame 10
(1, 0.5)
(2, 1.5)
(2, 1.5)
(4, 3) (4, 1.5)
(5, 2.5)
(5, 2.5)
(10, 5)
(3070, 11)
(1535, 10.5)
(1535, 10.5)
(1535, 9.5)
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Selection Criteria: Reconvergent Fanouts
The huge difference between the two costs is due to the reconverging fanout branches of the flip-flop.
Regular cost of a flip-flop with reconverging fanout branches should be adjusted to reduce the difference between the two costs
This can be done as follows. • Let g be a flip-flop with n fanout branches.
• Assume that m out of the n fanout branches reconverge at some gate in the circuit, then
• The regular cost of every one of these branches equals to the regular cost of g divided by m.
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Selection Criteria: Reconvergent Fanouts
C1 = 1
C1 = v
C1 = v/3 +1 C1 = 2v/3 +1
C1 = v+1
1
G1
G2
1
A
B
1G3
The three branches of stem B reconverge at gate G3
Thus, the regular cost of these branches will be divided by 3
The three branches of stem B reconverge at gate G3
Thus, the regular cost of these branches will be divided by 3
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Selection Criteria: Actual vs. General Values
Assuming general values on the gate inputs when computing the cost functions is less accurate than using the actual logical values.
C1=3
C1=1
C1=2
C1=3
G1
G4
11 1
0
11
1
1G3
G2
1
1
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Experimental Results
Experiments were performed on a number of ISCAS89 benchmarks.
Test sets generated by HITEC. Comparison between proposed technique and
bitwise-relaxation technique in terms of percentage of X’s and CPU time.
Experiments on Cost Functions.
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Proposed Tech. Vs Bitwise-Relaxation
The difference in the percentage of X’s ranges between 1% and 7%.
Average difference is about 3%.
Proposed Tech. vs Bitwise-Relaxation Tech.
0
20
40
60
80
100
1 2 3 4 5 6 7 8Benchmark Circuits
Per
cen
tag
e o
f X
's
Bitwise-RelaxationProposed Technique
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Proposed Tech. Vs Bitwise-Relaxation
CPU Time (sec)CPU Time (sec)
CircuitCircuitNameName
Proposed Proposed TechniqueTechnique
BitwiseBitwiseRelaxationRelaxation
S1423S1423 1.7501.750 943943
S1488S1488 2.4172.417 1255312553
S1494S1494 3.1003.100 1314613146
S3271S3271 8.0338.033 8772687726
S3330S3330 5.6335.633 115585115585
S3384S3384 2.5332.533 1654916549
S4863S4863 7.8007.800 162894162894
S5378S5378 20.3520.35 218137218137
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Effect of cost functions on % of X’s
CircuitCircuitNameName
A=0A=0B=0B=0
A=0A=0B=1B=1
A=1A=1B=0B=0
A=1A=1B=10B=10
A=1A=1B=30B=30
A=1A=1B=70B=70
A=1A=1B=90B=90
s1423s1423 37.88237.882 50.86350.863 57.05957.059 62.43162.431 63.68663.686 64.03964.039 63.02063.020
s1488s1488 44.44844.448 72.45772.457 56.62456.624 66.21866.218 69.96869.968 71.57171.571 72.24472.244
s1494s1494 43.51543.515 72.66172.661 57.41057.410 66.68766.687 70.50270.502 72.09872.098 72.74172.741
s3271s3271 57.36157.361 78.86078.860 82.06082.060 82.01782.017 82.03382.033 81.89281.892 81.90881.908
s3330s3330 66.54866.548 85.25185.251 84.80584.805 85.44685.446 85.40785.407 85.50685.506 85.50685.506
s3384s3384 69.24769.247 71.70371.703 77.75577.755 77.79977.799 77.78477.784 77.75577.755 77.75577.755
s4863s4863 72.11472.114 78.93478.934 83.40683.406 82.84682.846 82.58282.582 82.03882.038 81.73581.735
s5378s5378 77.78877.788 85.69285.692 82.13082.130 84.11084.110 85.05385.053 85.09485.094 86.05686.056
AVGAVG 58.61358.613 74.55374.553 72.65672.656 75.94475.944 77.12777.127 77.49977.499 77.62177.621
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Conclusions
A new test relaxation technique for synchronous sequential circuits.
Proposed technique is faster than the bitwise-relaxation method by several order of magnitude.
Percentage of X’s obtained close to those obtained by bitwise-relaxation for most of the circuits.
Does not do any optimization in selecting POs for fault detection. This will be investigated in future work.