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AHB-LiteTimer
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AHB-LiteTimerDatasheet
AHB-LiteTimer
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IntroductionTheRoaLogicAHB-LiteTimerIPisafullyparameterizedsoftIPimplementingauser-defined number of timers and functions as specified by the RISC-VPrivileged1.9.1specification.
TheIPfeaturesanAHB-LiteSlaveinterface,withallsignalsdefinedintheAMBA3 AHB-Lite v1.0 specifications fully supported, supporting a single AHB-Litebased host connection. Bus address & data widths as well as the number oftimerssupportedarespecifiedviaparameters.
ThetimebaseofthetimersisderivedfromtheAHB-Litebusclock,scaleddownbyaprogrammablevalue.
Themodule features a single Interrupt outputwhich is assertedwhenever anenabledtimeristriggered
Figure1:AHB-LiteTimer
Features
• AHB-LiteInterfacewithprogrammableaddressanddatawidth• Userdefinednumberofcounters(Upto32)• ProgrammabletimebasederivedfromAHB-Litebusclock
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TableofContentsIntroduction...........................................................................................................2Features..................................................................................................................................................................21 GettingStarted.................................................................................................41.1 Deliverables..............................................................................................................................................41.2 Runningthetestbench.........................................................................................................................51.2.1 Self-checkingtestbench...................................................................................................................51.2.2 Makefilesetup......................................................................................................................................51.2.3 Makefilebackup..................................................................................................................................51.2.4 NoMakefile...........................................................................................................................................5
2 Specifications....................................................................................................62.1 FunctionalDescription.........................................................................................................................6
3 Configurations..................................................................................................73.1 Introduction..............................................................................................................................................73.1 CoreParameters.....................................................................................................................................73.1.1 TIMERS...................................................................................................................................................73.1.2 HADDR_SIZE.........................................................................................................................................73.1.3 HDATA_SIZE.........................................................................................................................................7
3.2 CoreRegisters..........................................................................................................................................73.2.1 PRESCALER...........................................................................................................................................73.2.2 IPENDING..............................................................................................................................................83.2.3 IENABLE.................................................................................................................................................83.2.4 TIME.........................................................................................................................................................83.2.5 TIMECMP[n].........................................................................................................................................9
4 Interfaces........................................................................................................104.1 AHB-LiteInterface...............................................................................................................................104.1.1 HRESETn..............................................................................................................................................104.1.2 HCLK......................................................................................................................................................104.1.3 HSEL.......................................................................................................................................................104.1.4 HTRANS................................................................................................................................................114.1.5 HADDR..................................................................................................................................................114.1.6 HWDATA..............................................................................................................................................114.1.7 HRDATA................................................................................................................................................114.1.8 HWRITE................................................................................................................................................114.1.9 HSIZE.....................................................................................................................................................114.1.10 HBURST..............................................................................................................................................114.1.11 HPROT................................................................................................................................................124.1.12 HREADYOUT....................................................................................................................................124.1.13 HREADY.............................................................................................................................................124.1.14 HRESP.................................................................................................................................................12
4.2 TimerInterface.....................................................................................................................................134.2.1 TIMER_INTERRUPT.........................................................................................................................13
5 Resources.......................................................................................................14
6 RevisionHistory..............................................................................................15
AHB-LiteTimer
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1 GettingStarted1.1 DeliverablesAll IP isdeliveredasazipped tarball,whichcanbeunzippedwithall commoncompressiontools(likeunzip,winrar,tar,…).
Thetarballcontainsadirectorystructureasoutlinedbelow.
Figure1-1:IPDirectoryStructure
The doc directory contains relevant documents like user guides, applicationnotes,anddatasheets.
The rtl directory contains the actual IP design files. Depending on the licenseagreement theAHB-LiteTimer isdeliveredaseitherencryptedVerilog-HDLorasplainSystemVerilogsourcefiles.Encryptedfileshavetheextension“.enc.sv”,plainsourcefileshavetheextension“.sv”.Thefilesareencryptionaccordingtothe IEEE-P1735 encryption standard. Encryption keys for Mentor Graphics(Modelsim,Questasim,Precision), Synplicity (Synplify, Synplify-Pro), andAldec(Active-HDL, Riviera-Pro) are provided. As such there should be no issuetargetinganyexistingFPGAtechnology.
Ifanyothersynthesisoranalysis tool isused thenaplainsourceRTLdeliverymay be needed. A separate license agreement andNDA is required for such adelivery.
Thebenchdirectorycontainsthe(encrypted)sourcefilesforthetestbench.
doc
rtl
verilog
sim
rtlsim
bin
run
bench
verilog
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Thesimdirectorycontainsthefiles/structuretorunthesimulations.Section1.2‘Runningthetestbench’providesforinstructionsonhowtousethemakefile.
1.2 Runningthetestbench
TheAHB-LiteTimerIPcomeswithadedicatedtestbenchthattestsallfeaturesofthe design and finally runs a full random test. The testbench is started fromaMakefilethatisprovidedwiththeIP.
The Makefile is located in the <install_dir>/sim/rtlsim/run directory. TheMakefile supports most commonly used simulators; Modelsim/Questasim,Cadencencsim,AldecRiviera,andSynopsysVCS.
To start the simulation, enter the <install_dir>/sim/rtlsim/run directory andtype: make <simulator>. Where simulator is any of: msim (formodelsim/questasim), ncsim (for Cadence ncsim), riviera (for Aldec Riviera-Pro), or vcs (for Synopsys VCS). For example typemake msim to start thetestbenchinModelsim/Questasim.
1.2.1 Self-checkingtestbench
The testbenches is a self-checking testbench intended tobe executed from thecommand line. There is no need for a GUI or a waveform viewer. Once thetestbenchcompletesitdisplaysasummaryandclosesthesimulator.
1.2.2 Makefilesetup
The simulator is executed in its associated directory. Inside this directory isanotherMakefilethatcontainssimulatorspecificcommandstostartandexecutethe simulation. The <install_dir>/sim/rtlsim/run/Makefile enters the correctdirectoryandcallsthesimulatorspecificMakefile.
For example modelsim is executed in the <install_dir>/sim/rtlsim/run/msimdirectory. Typingmakemsim loads themainMakefile,which then enters themsimsub-directoryandcallsitsMakefile. ThisMakefilecontainscommandstocompile the RTL and testbench sources with Modelsim, start the Modelsimsimulator,andrunthesimulation.
1.2.3 Makefilebackup
The <install_dir>/sim/rtlsim/bin directory contains backups of the originalMakefiles.ItmaybedesirabletomodifyorextendtheMakefilesortocompletelycleantherundirectory.Usethebackupstorestoretheoriginalsetup.
1.2.4 NoMakefile
For users unfamiliar with Makefiles or those on systems that do not nativelysupport make (e.g. Windows) a run.do file is provided that can be used withModelsim/QuestasimandRiviera-Pro.
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2 Specifications2.1 FunctionalDescriptionTheAHB-LiteTimerIPisafullyparameterisedTimer-tickcore,featuringasingleAHB-LiteSlaveinterfaceandasinglemultiplexedInterruptoutputsignal.
TheTimerIPisintendedtogenerateCPUinterruptsatregulartimeintervals,fortimedeventssuchastimekeeping,task/contextswitches,andsleep().
Thenumberof timersandAddress&Datawidthof theAHB-Lite interfacearespecifiedviaparametersdefinedatcompiletime.
Thetimebaseof thetimers iscommontoall timersanddefinedatruntimebywritingtothePRESCALERregister.IndividualtimeralarmsmaythensetviatheTIMECMP[n]registers.All timersarepermanentlyenabledhoweveraseparateIENABLEregisterallowsanytriggeredcounteroutputtobemasked.
The usermay determine both the status of theTIMERS includingwhich timerhasgeneratedaninterruptviaareadoperationtotheAHB-Liteinterface.
Figure2-1:AHB-LiteTimerSystemDiagram
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AHB-LiteTimer
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3 Configurations3.1 IntroductionThe size and implementation style of the timer module is defined via HDLparametersasspecifiedbelow.
3.1 CoreParameters
Parameter Type Default DescriptionTIMERS Integer 3 NumberofTimersHADDR_SIZE Integer 32 WidthofAHB-LiteAddressBusHDATA_SIZE Integer 32 WidthofAHB-LiteDataBuses
Table3-1:CoreParameters
3.1.1 TIMERS
TheparameterTIMERSdefinesthenumberoftimerssupportedandtherebythenumberofTIMECMP registers implementedbythecore.Valuesbetween1and32aresupported,withthedefaultdefinedas‘3’.
3.1.2 HADDR_SIZE
TheHADDR_SIZE parameter specifies the address bus size to connect to theAHB-Litebasedhost.
3.1.3 HDATA_SIZE
TheHDATA_SIZEparameterspecifiesthedatabussizetoconnecttotheAHB-Litebasedhost.Themaximumsizesupportedis64bits.
3.2 CoreRegisters
Register Address Size Access FunctionPRESCALER Base+0x00 32bits Read/Write TimebaseIPENDING Base+0x08 32bits ReadOnly InterruptPendingIENABLE Base+0x0C 32bits Read/Write InterruptEnableTIME Base+0x10 64bits Read/Write TimerRegisterTIMECMP[n] Base+0x18+8n 64bits Read/Write CompareValueNote:‘n’representsanintegerfor0toTIMERS-1.
3.2.1 PRESCALER
The Timermodule operates synchronously with the AHB-Lite bus clock inputHCLK.A32bitPRESCALER registerenables thetimebase for thetimerstobe
AHB-LiteTimer
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less than that of HCLK by dividing this clock frequency by the value ofPRESCALER + 1.
Forexample:IfPRESCALER=3,thetimerwillincrementeveryPRESCALE+1=4cyclesofHCLK,settingthetimebasetoHCLK/4Hz.
Thedefault value ofPRESCALER=0, thereby setting the timer clock frequencyequaltothebus(HCLK)frequency.TheTIMEcounterstartsincrementingoncetheregisterPRESCALERiswrittentoforthefirsttime(Seesection3.2.4).
Note: The value of PRESCALER value can only be defined once after theperipheralisreleasedfromreset.
3.2.2 IPENDING
IPENDING is a 32-bit read-only register that indicates if a timer interrupt ispending.
EachbitoftheIPENDINGregistercorrespondstoonetimerwiththepositionofeach bit indicating the associated timer. E.g. bit zero indicates the interruptstatus of Timer[0].IPENDING bits associatedwith unimplemented timers aretiedlow(‘0’)
AninterruptpendingbitissetwhenthevalueofTIMECMP[n]equalsthevalueof TIME. It is cleared by a write to the associated TIMECMP[n] register, asspecifiedintheRISC-Vprivilegedspec1.9.1.
3.2.3 IENABLE
IENABLE is a 32-bit Read/Write register, where each bit of the register is adedicated 'Interrupt Enable' bit for each time. The bit position indicates theassociatedtimer.E.g.InterruptEnableforTimer[0]islocatedatbitposition0.
OnlyTIMERSbitsareimplementedwiththeremainingMSBsalwaysreadas'0'.AwritetotheunusedMSBshasnoeffect.
An interrupt is generated when a bit of IPENDING is set and its associatedIENABLEbitisalsoset.Thisallowsthecoretobeusedin(1)purePOLLmode,wheretheCPUpollsthestatusofthebitstodetermineifatimereventhappened,(2)pureinterruptdrivenmode,whereeachtimercangenerateaninterrupt,or(3)acombinationoftheabove.
3.2.4 TIME
The TIME register is a common 64-bit high-resolution time-keeping counterusedbyalltimers.ItisthebasisfortheRDCYCLEinstructionasspecifiedinthe
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RISC-Vprivilegedspec1.9.1andmaybewrittentoalso inaccordancewiththeRISC-Vspecification.
The time base for the TIME register is derived from the AHB-Lite bus clockHCLK,asdescribedinsection3.2.1,andisdefinedas:
FreqTIME = FreqHCLK / (PRESCALER+1)
ThecounterstartsincrementingoncetheregisterPRESCALER iswrittentoforthefirsttime.
3.2.5 TIMECMP[n]
Foreachtimer(asdefinedbytheparameterTIMER)thereisadedicated64bitTimeCompareregisterwhichdefineswhentheIPENDINGbitsareasserted
These registers are denoted asTIMECMP[n], where ‘n’ is an index from 0 toTIMERS-1,andarelocatedconsecutivelyintheaddressspaceaccordingtotheformula:
Base Address of TIMECMP[n] = 0x18 + 8n
For example,TIMECMP[0] is located at address 0x18,TIMECMP[1] at 0x20,TIMECMP[1]at0x28etc.
TheIPENDINGbitassociatedwiththeTIMECMPregisterissetwhentheTIMECMP[n]valueequalsthevalueofTIME. IPENDING[n] = (TIMECMP[n] == TIME) WritingtheTIMECMP[n]registerclearsbit‘n’oftheIPENDINGregister.
AHB-LiteTimer
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4 Interfaces4.1 AHB-LiteInterfaceTheAHB-LiteinterfaceisaregularAHB-Liteslaveport.Allsignalsaresupported.SeetheAMBA3AHB-LiteSpecificationforacompletedescriptionofthesignals.
Port Size Direction DescriptionHRESETn 1 Input AsynchronousactivelowresetHCLK 1 Input ClockInputHSEL 1 Input BusSelectHTRANS 2 Input TransferTypeHADDR HADDR_SIZE Input AddressBusHWDATA HDATA_SIZE Input WriteDataBusHRDATA HDATA_SIZE Output ReadDataBusHWRITE 1 Input WriteSelectHSIZE 3 Input TransferSizeHBURST 3 Input TransferBurstSizeHPROT 4 Input TransferProtectionLevelHREADYOUT 1 Output TransferReadyOutputHREADY 1 Input TransferReadyInputHRESP 1 Output TransferResponse
Table4-1:AHB-LiteInterfacePorts
4.1.1 HRESETn
WhentheactivelowasynchronousHRESETninputisasserted(‘0’),theinterfaceisputintoitsinitialresetstate.
4.1.2 HCLK
HCLKistheinterfacesystemclock.AllinternallogicfortheAMB3-LiteinterfaceoperatesattherisingedgeofthissystemclockandAHBbustimingsarerelatedtotherisingedgeofHCLK.
4.1.3 HSEL
The AHB-Lite interface only responds to other signals on its bus – with theexception of the global asynchronous reset signal HRESETn – when HSEL isasserted(‘1’).WhenHSELisnegated(‘0’)theinterfaceconsidersthebusIDLE.
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4.1.4 HTRANS
HTRANSindicatesthetypeofthecurrenttransfer.
HTRANS Type Description00 IDLE Notransferrequired01 BUSY Connectedmasterisnotreadytoacceptdata,but
intentstocontinuethecurrentburst.10 NONSEQ Firsttransferofaburstorasingletransfer11 SEQ Remainingtransfersofaburst
Table4-2:AHB-LiteTransferType(HTRANS)
4.1.5 HADDR
HADDRistheaddressbus.ItssizeisdeterminedbytheHADDR_SIZEparameterandisdriventotheconnectedperipheral.
4.1.6 HWDATA
HWDATA is the write data bus. Its size is determined by the HDATA_SIZEparameterandisdriventotheconnectedperipheral.
4.1.7 HRDATA
HRDATAisthereaddatabus.ItssizeisdeterminedbyHDATA_SIZEparameterandissourcedbytheAPB4peripheral.
4.1.8 HWRITE
HWRITE is the read/write signal. HWRITE asserted (‘1’) indicates a writetransfer.
4.1.9 HSIZE
HSIZEindicatesthesizeofthecurrenttransfer.
HSIZE Size Description000 8bit Byte001 16bit HalfWord010 32bit Word011 64bits DoubleWord100 128bit 101 256bit 110 512bit 111 1024bit
Table4-3:TransferSizeValues(HSIZE)
4.1.10 HBURST
HBURSTindicatesthetransactionbursttype–asingletransferorpartofaburst.
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HBURST Type Description000 SINGLE Singleaccess001 INCR Continuousincrementalburst010 WRAP4 4-beatwrappingburst011 INCR4 4-beatincrementingburst100 WRAP8 8-beatwrappingburst101 INCR8 8-beatincrementingburst110 WRAP16 16-beatwrappingburst111 INCR16 16-beatincrementingburst
Table4-4:AHB-LiteBurstTypes(HBURST)
4.1.11 HPROT
TheHPROTsignalsprovideadditionalinformationaboutthebustransferandareintendedtoimplementalevelofprotection.
Bit# Value Description3 1 Cacheableregionaddressed 0 Non-cacheableregionaddressed2 1 Bufferable 0 Non-bufferable1 1 PrivilegedAccess 0 UserAccess0 1 DataAccess 0 Opcodefetch
Table4-5:AHB-LiteTransactionProtectionSignals(HPROT)
4.1.12 HREADYOUT
HREADYOUT indicatesthatthecurrenttransferhasfinished.Note,fortheAHB-LiteTimerthissignalisconstantlyassertedasthecoreisalwaysreadyfordataaccess.
4.1.13 HREADY
HREADY indicateswhetherornottheaddressedperipheral isreadytotransferdata. When HREADY is negated (‘0’) the peripheral is not ready, forcing waitstates.WhenHREADY is asserted (‘1’) theperipheral is ready and the transfercompleted.
4.1.14 HRESP
HRESP is the instruction transfer response and indicatesOKAY (‘0’) orERROR(‘1’).
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4.2 TimerInterface
4.2.1 TIMER_INTERRUPT
TIMER_INTERRUPT is a single output signal that is asserted the followingconditionsarebothmet:
1. AnybitoftheIPENDINGregisterisasserted2. ThecorrespondingbitoftheIENABLEregisterisalsoasserted.
Thismayalsobewrittenas:
TIMER_INTERRUPT <= IPENDING & IENABLE
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5 ResourcesBelowaresomeexampleimplementationsforvariousplatforms.
All implementations arepushbutton, no efforthasbeenundertaken to reduceareaorimproveperformance.
Platform DFF LogicCells
Memory Performance(MHz)
Table5-1:ResourceUtilizationExamples
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6 RevisionHistoryDate Rev. Comments 1.0
Table6-1:RevisionHistory