Post on 18-Dec-2015
Advance Nano Device Lab. 1
Fundamentals of Modern VLSI Devices 2nd EditionYuan Taur and Tak H.Ning
Ch5. CMOS Performance Factors
Advance Nano Device Lab. 2
Ch5.1 Basic CMOS Circuit Elements
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CMOS Inverters
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CMOS Inverter Transfer Curve
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CMOS Inverter Transfer Curve
(5.1)
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CMOS Inverter Noise Margin
(5.2)
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CMOS Inverter Noise Margin
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CMOS Inverter Noise Margin
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CMOS Inverter Switching Characteristics
(5.3)
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CMOS Inverter Switching Characteristics
(5.4) (5.5)
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Switching Energy and Power Dissipation
(5.6)
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Quasistatic Assumption
(5.7)
(5.8)
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CMOS NAND and NOR Gates
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Two-Input CMOS NAND Gate
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Two-Input CMOS NAND Gate
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Noise Margin of NAND Circuits
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Layout of a Single Device
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Layout of a CMOS Inverter
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Layout of a Two-Input CMOS NAND
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Ch5.2 Parasitic Elements
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Source-Drain Resistance
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Accumulation-Layer Resistance and Spreading Resistance
(5.9)
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Sheet Resistance
(5.10)
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Contact Resistance
(5.11)
(5.12)
(5.13)
(5.14)
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Resistance in a Self-Aligned Silicide Technology
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Parasitic Capacitances
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Junction Capacitance
(5.15)
(5.16)
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Overlap Capacitance
(5.17)
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Overlap Capacitance
(5.18)
(5.20)
(5.19)
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Gate Resistance
(5.21) (5.22)
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Gate Resistance
(5.23)
(5.24)
(5.25)
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Gate Resistance
(5.26)
(5.27)
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Gate Resistance
(5.28)
(5.29)
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Interconnect R and C
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Interconnect R and C
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Interconnect R and C
(5.30)
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Interconnect Scaling
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Interconnect Scaling
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Interconnect Resistance
(5.31)
(5.32)
(5.33)
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RC Delay of Global Interconnects
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RC Delay of Global Interconnects
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Ch5.3 Sensitivity of CMOS Delay to Device Parameters
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Propagation Delay of a CMOS Inverter Chain
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Propagation Delay of a CMOS Inverter Chain
(5.34)
(5.35)
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Propagation Delay of a CMOS Inverter Chain
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Bias-Point Trajectories in a Switching Event
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Bias-Point Trajectories in a Switching Event
(5.36)
(5.37)
(5.38)
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Delay Equation: Switching Resistance, Input and Output Capacitance
(5.39)
(5.40)
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Delay Equation: Switching Resistance, Input and Output Capacitance
(5.41)
(5.42)
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CMOS Delay Sensitivity to pMOSFET/nMOSFETwidth ratio
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Device Width Effect with Respect to Load Capacitance
(5.43)
(5.44)
(5.45)
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Sensitivity of Delay to Channel Length
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Sensitivity of Delay to Gate Oxide Thickness
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Sensitivity of Delay to Power-Supply Voltage and Thresh-old Voltage
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Power and Delay Tradeoff
(5.46)
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Sensitivity of Delay to Series Resistance
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Sensitivity of Delay to Overlap Capacitance
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Miller Effect
(5.47)
(5.48)
(5.49)
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Sensitivity of Delay to Junction Capacitance
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Sensitivity of Delay to Junction Capacitance
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Top and Bottom Switching of a Two-Way NAND Gate
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Top and Bottom Switching of a Two-Way NAND Gate
(5.50)
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Ch5.4 Performance Factors of Advanced CMOS Devices
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Small-Signal Equivalent Circuit
(5.51)
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Small-Signal Equivalent Circuit
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Unity-Current-Gain Frequency of an Intrinsic MOSFET
(5.52)
(5.53)
(5.54)
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Unity-Current-Gain Frequency of an Intrinsic MOSFET
(5.55)
(5.56)
(5.57)
Advance Nano Device Lab. 69
Effect of Transport Parameters on CMOS Performance
(5.58)
(5.59)
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Low-Temperature CMOS
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Low-Temperature CMOS