4. Combinational Logic Networks. 4.2 Layout Design Methods 4.2.1 Single Row Layout Design Power...

Post on 17-Jan-2016

231 views 0 download

Transcript of 4. Combinational Logic Networks. 4.2 Layout Design Methods 4.2.1 Single Row Layout Design Power...

4. Combinational Logic Networks.4.2 Layout Design Methods4.2.1 Single Row Layout Design

•Power rails•Routing chnnel•n-type, p-type row

Intra-rowRouting area

• Horizontal tracks and vertical tracks

• Channel Density, changed with pin assignment.(below)

Structure of a routing channel

Layout of a full adder • Swap the gates within each function

• Swap the XOR pair with NAND networks

• Optimum under assumption that only one horizontal wire segment per net.

Left-edge channel routing

Channel that cannot be routed by the left edge algorithm(Vertical constraint)

A dogleg wire

• Cell from libraryNAND, NOR, AOI, OAI

• The same pitch (height)• VDD and VSS lines must mat

ch up.• External connection points ar

e on the top and bottom edges.

• Cell area cannot be used for wiring.

• Feedthrough area for short cut of critical pathes.

• Transistor sizes are typically much larger than those in custom layouts.

4.2.2 Standard Cell Layout Design

Wireability of placement

• Rat’s nest plot to identify congested area, whose degree of congestion will be minimized.

4.3 Simulation

•Circuit Simulation•Timing Simulation•Switch Simulation•Gate Simulation (Logic Simulation)

a 1

b 0

c 0

d 1

o 1

a 1

b 1

c 0

d 1

o 0

Propagate new valueuntil it will be stable

• Transistors of driving gate can be enlarged.

• Logic can be redesigned to reduce the gate’s fanout.

4.4 Combinational Network Delay4.4.1 Fanout

• Timing Analysis identifies critical path with graph model, instead of exhausted search with logic simulator.

4.4.2 Path Delay

Cutset of critical path: increase transistor size reduce wire capacitance

Critical Path

• True Path determines

timing constraint.

False Path

Redesign for speed up

a(b+c(d+ef))

ab+acd+acef

4.4.3 Transistor Sizing

• 0.5nsec delay/stage

1

1

0

0

1

All n: 0.75/0.5

All p: 1.5/0.5

Transistor Sizing (Continue)

• 0.25nsec delay/stage2 times as faster as before

1

1

0

0

1

Pull up: 1.5/0.5 4.5/0.5 (first stage)

3.0/0.5(other stages)

0.75/0.5 1.5/0.5

Pull down: 0.75/0.5 1.5/0.5

Transistor Sizing (Continue)

• 0.125nsec delay/stage4 times as faster as before

1

1

0

0

1

Pull up: 1.5/0.5 4.5/0.5 (first stage)

3.0/0.5(other stages)

0.75/0.5 3/0.5

Pull down: 0.75/0.5 1.5/0.5

• Crosstalk depend on

1) Adjacent area2) Behavior of 2

signals

4.5 Crosstalk

• Ground wires to minimize crosstalk

Crosstalk (continue)

• Crosstalk minimization by wire routing

Crosstalk (continue)

Total coupling=17 Total coupling=12(a-b=6, b-c=6, c-d=5) (a-b=5, a-d=2, d-c=5)

4.6 Power Optimizationby reducing glitches

Glitch power

• Glitches propagate through the successive stage. the longer chain produces much glitch.

• Signal probability Ps: the probability that signal s is 1.

• Probability of a transition Ptr,s: the probablity that signal changes from 0 to 1 or from 1 to 0.

Ptr,s=(1-Ps)Ps+Ps(1-Ps)=2Ps(1-Ps)

• Power estimation tools based on delay independent assumption

PNOT=1-Pin

POR=1-(1-Pin1)(1-Pin2)

PAND=Pin1 Pin2

Power Optimization (continue)

Logic factorization for low power

Switch network with non-constant source inputs.

4.7 Switch Logic Networks

Swicth implementation of a multiplexer

Switch Logic is not universally useful.• Slow• introduce hard-to-trace electrical problems• lack of drive current for high capacitive load

Switch Logic Networks (continue)

10 10 10

10

Output remains 11(Output should be undefined)

• Voltages are dependent on capacitance ratios, which cannot be controlled.

• Table shows possible voltage

change of nodes.

time i Cia a Cab b Cbc c Cco

0 1 1 1 1 1 1 1 1

1 0 0 1 0 0 1 0 1

2 0 0 0 0.5 1 0.5 0 1

3 0 0 0 0.5 0 0.75 1 0.75

4 0 0 1 0 0 0.75 0 0.75

5 0 0 0 0.375 1 0.375 0 0.75

• Voltages are dependent on capacitance ratios, which cannot be controlled.

• Table shows possible voltage

change of nodes.

time i Cia a Cab b Cbc c Cco

0 1 1 1 1 1 1 1 1

1 0 0 1 0 0 1 0 1

2 0 0 0 0.5 1 0.5 0 1

3 0 0 0 0.5 0 0.75 1 0.75

4 0 0 1 0 0 0.75 0 0.75

5 0 0 0 0.375 1 0.375 0 0.75

Switch Logic Networks (continue)Charge Sharing

• fault model (stuck-at-0/1)

4.8.1 Gate Testing

a b Fault-free

S-a-0

S-a-1

0 0 1 0 1

0 1 0 0 1

1 0 0 0 1

1 1 0 0 1

a b Fault-free

S-a-0

S-a-1

0 0 1 0 1

0 1 1 0 1

1 0 1 0 1

1 1 0 0 1

NAND NOR

Gate Testing (Continue)

0

1

11

Vector(011) for 2 NANDs stuck-at-0 test

Vector(11-)(-01) for 2 NANDs stuck-at-1 test

1

1

1

-

-

0

1

• t1 stuck-open faultmakes gate not topull up to VDD.

• t2 stuck-open faultmakes gate pull down to VSS, conditionally.

• Delay fault• Gate delay fault• Path delay fault

Stuck-Open fault

• Controlling the gate’s inputs by applying values to the network’s primary inputs.

• Observing the gate’s output by inferring its value from the values at the network’s primary outputs.

4.8.2 Combinational Network Testing

Stuck-at-0

Job1: either 1must be set.

Job2: Dout 0 or 1 to be observed at primary output.

• NOR output sa0 (“1”) cannot be set.

• NAND output sa0 (“1”) cannot be observed at primary output.

• F=[(ab)’+b] =[a+b’+b] =0

Fault Masking

Logic is untestable,Because of rudundant.