Post on 13-Apr-2015
STM32 Seminar STM32F G l P LiSTM32F General Purpose Lines
COMPEL/STM SeminarCOMPEL/STM SeminarNovember 2010
Seminar AgendaOverview of ST Microcontroller PortfolioIntroduction to Cortex-M Core STM32 General Purpose Lines
Product-Line Overview (F100/F101/F103)Walk through the main peripheralsST Standard Peripheral LibraryLive demonstration of the STM32 Value Discovery Kit
STM32 Low Power LineSTM32 Low-Power LineProduct-Line Overview (L15x)Low-Power modes and consumption Specific Peripherals
STM32 Connectivity LineSTM32 Connectivity LineProduct-Line Overview (F105/7 & next)Ethernet & USB Host PeripheralsThird Party StacksAudio Supportpp
STM32 WirelessProduct-Line Overview (W108)RF PerformancesWireless Stacks (Zigbee, RF4CE, proprietary)
STM32 ToolsThird Party Compiler & IDEBoards and DebugerST Libraries
STM32 Seminar November 2010
STM32F10x Product LinesAll lines include:
Multiple communication peripheralsUp to 5 x USART, 3xSPI, 2xI²C
Up to 256 KB Flash /
64KB SRAM
2 x CAN
USB 2.0 OTG (FS)
PWM
timer
2x12-bit ADC(1µs)
TempSensor
72MHz CPU
Connectivity Line: STM32F107
2 x Audio Class I2S
Ethernet IEEE158
8
Dual 12-bit DAC***
FSMC**
ETM*
Up to 256 KB Flash /
64KB SRAM
2 x CAN
USB 2.0 OTG (FS)
PWM
timer
2x12-bit ADC(1µs)
TempSensor
72MHz CPU
Connectivity Line: STM32F1052 x Audio Class I2S
Up to 1MB Flash /
96KB SRAMCANUSB–FS
DevicePWM
timer
2/3x12-bit ADC(1µs)
TempSensor
72MHz CPU
Performance Line: STM32F103Main Osc 4-16MHz (25MHz on 105/107)
Multiple 16-bit Timers
I t l 8 MH RCSDIO* I2S*
TempSensorInternal 8 MHz RCand 40 kHz RC
Real Time Clock with Battery domain & 32KHz ext osc 1x12-bit ADC
(1µs)T
48MHz CPU
Up to 128KB Flash / 16KB
SRAM
USB Access Line: STM32F102
USB–FS Device
1x12-bit ADC (1µs)36MHz
CPU
Up to 1MB Flash / 80KB
SRAM
Access Line: STM32F101
Up to 12 DMA cnls
2 x Watchdogs
Reset circuitry andBrown Out Warning
Temp sensorSRAM
Temp sensorCPU SRAMUp to 12 DMA cnls
* Performance/Access Lines 256KB, 384KB, or 512KB devices and ALL Connectivity devices
1x12-bit ADC (1 2µs)24MHz Up to 512KB
Flash / 32KB
Value Line: STM32F100** 256KB, 384KB, or 512KB Performance and Access devices HDMI-
CECPWM
STM32 Seminar November 2010
(1.2µs)Temp sensor
CPU Flash / 32KB SRAM
CEC timer*** 256KB, 384KB, or 512KB devices except Value line where present on all memory range
STM32 General Purpose PortfolioFlash
(bytes)
STM32F103/1RE STM32F103/1VE STM32F103/1ZE
STM32F103/1RE STM32F103/1VE STM32F103/1ZE
768 K1 MB
512 K
384 K STM32F103/1RD
STM32F100RESTM32F103/1RE
Connectivity line
Performance STM32F103/1VD STM32F103/1ZD
STM32F100VESTM32F103/1VE
STM32F100ZESTM32F103/1ZE
STM32F103/1RE STM32F103/1VE STM32F103/1ZE768 K
PIN
256 K
384 K STM32F100RD
Value line
and Access line
STM32F100RCSTM32F103/1RCSTM32F105/7RC
STM32F100VCSTM32F103/1VC
STM32F100ZCSTM32F103/1ZC
STM32F100VD STM32F100ZD
STM32F105/7VC
TO P
IN C
128 K
STM32F105R8
STM32F100RBSTM32F103/2/1RBSTM32F105/7RB
STM32F100CBSTM32F103/2/1CB
STM32F101VBSTM32F103VB
STM32F105/7VB
STM32F105V8
CO
MPAT
32 K
64 K
STM32F100R6STM32F103R6
STM32F100R8STM32F103/2/1R8
STM32F105R8
STM32F103/2/1C6STM32F103/1T6
STM32F100C8STM32F103/2/1C8STM32F103/1T8
STM32F100V8STM32F103/1V8
STM32F105V8
CortexTM-M3 CPU4 t 64 Kb t SRAMSTM32F100C6
TIBLE
100 i64 i48 i 144 i36 i
16 K STM32F100R4STM32F103/2/1R4
STM32F100R6
STM32F100C4STM32F103/2/1C4STM32F103/1T4
– 4- to 64-Kbyte SRAM– 6 lines– Full compatibility
across 115part numbers
STM32F100C6
STM32 Seminar November 2010
100 pins LQFP
64 pins LQFP/BGA(1)
48 pinsLQFP
144 pins LQFP/BGA(1)
36 pinsQFN
STM32’s I/O peripheralsHigh-performance analog
12-bit ADC with 1 µs conversion12-bit DAC*12 bit DAC
General-purpose I/OFully configurableFully configurable18 MHz max toggle rate
Advanced timersAdvanced timersMulti-mode 16-bit timersMotor control timers*Watchdog and SysTick timersWatchdog and SysTick timersReal-time clock with battery backup
STM32 Seminar November 2010*Device dependant
STM32’s connectivity and system peripheralsConnectivity
4.5 Mbit/s USARTs18 Mbit/s SPI with18 Mbit/s SPI with SDIO support*400 kHz I²CUSB de ice*USB device*CAN*I²S*USB OTG*USB OTG*Ethernet*
S t i h lSystem peripherals12-channel DMA controller*Flexible system memory controller (FSMC)*
STM32 Seminar November 2010*Device dependant
STM32 maximum integrationClocks
Advanced PLLs for single Xtal operation or coreand peripheralsa d pe p e a sAccurate RC oscillator with trimming register
Reset circuitryReset circuitryPower-on resetLow-voltage detect (brown-out)Watchdog timersWatchdog timers
System securityTamper detectTamper detect
Power managementI t t d l lt l t f i l 2 0 V tIntegrated low-voltage regulator for single 2.0 V to3.3 V operationClock enable/disable for each peripheral
STM32 Seminar November 2010
STM3210x low-power characteristicsTyp @ 25 °C
Low-voltage 2.0 V to 3.6 V operation
<14 µA Run mode ~ 0.5 mA/MHz 0.27 mA/MHz peripheral off
Startup time from stop <6 µs
3.4 µA
Startup time from stop <6 µsStartup time from standby 50 µs
µ
Stop
Stop - All clocks off, reset active, RAM on (register content preserved)
0 9 A
2 µA
Standby
RTC off
Standby- All clocks off, reset active, RAM
off but 20 bytes available for backup
Standby
RTC on
0.9 µARTC
Vbat
RTC off
STM32 Seminar November 2010
STM32F103 Performance Line
• 2-channel 12-bit DAC
CORTEXTM-M3 CPU
72 MHzPower Supply
Reg 1.8VPOR/PDR/PVD
z)
Flas
h I/F 256kB - 512kB
Flash Memory
• FSMC
• ETMJTAG/SW Debug
i-Spe
ed B
us(m
ax 3
6/ 7
2MH
z
ETM
XTAL oscillators32KHz + 4~16MHz
Int. RC oscillators
32kB - 64kB SRAM
84B Backup DataETM
• SDIO
• I²S
FSMCSRAM/ NOR/NAND/CF/ LCD parallel interface
DMAup to 12 Channels
Nested vect IT Ctrl
1 x Systick Timer
AR
M ®
Lite
Hat
rix /
Arb
iter
RTC / AWU
ETM40KHz + 8MHz
PLL
Clock Control• I²S
• 12 channels DMA
2 PWM ti s
1 x USB 2.0FS
1 x CAN 2.0B2 x 16-bit PWM
up to 12 Channels
Bridge
Bridge
AM
a
ARM® Peripheral Bus(max 36MHz)
SDIOSD/SDIO/MMC/CE-ATA
Clock Control
6 16 bi Ti• 2xPWM timers
• 3xADCs
Perip
hera
l Bus
ax 7
2MH
z)
4 x USART/LINSmartcard / IrDaM d C t l
Up to 112 I/Os
Up to 16 Ext. ITs
1 x CAN 2.0BSynchronized AC Timer
2 x SPI / I²S
2-channel 12-bit DAC
2 x Watchdog(independent & window)
6 x 16-bit Timer
• Up to 112 I/Os (144 pins package)
AR
M®
P(m
a
2 x I2C
Modem Control
1 x USART/LINSmartcard/IrDaModem Control
1 x SPI3 x 12-bit ADC / 1Msps
up to 21 channels
Temperature Sensor
STM32 Seminar November 2010
STM32F103 Access Line
• 2-channel 12-bit DAC
CORTEXTM-M3 CPU
36 MHzPower Supply
Reg 1.8VPOR/PDR/PVD
z)
Flas
h I/F 256kB - 512kB
Flash Memory
• FSMC
• ETMJTAG/SW Debug
i-Spe
ed 3
6us
(max
36/
72M
Hz
ETM
XTAL oscillators32KHz + 4~16MHz
Int. RC oscillators
4kB - 48kB SRAM
84B Backup DataETM
• 12 channels DMA
• Up to 112 I/Os (144
FSMCSRAM/ NOR/NAND/CF/ LCD parallel interface
DMAup to 12 Channels
Nested vect IT Ctrl
1 x Systick Timer
AR
M ®
Lite
Hi
atrix
/ A
rbite
r
RTC / AWU
ETM40KHz + 8MHz
PLL
Clock Control• Up to 112 I/Os (144 pins package)
s
up to 12 Channels
Bridge
Bridge
A Ma
ARM® Peripheral Bus(max 36MHz)
Clock Control
6 16 bi Ti
Perip
hera
l Bus
ax 3
6MH
z)
4 x USART/LINSmartcard / IrDaM d C t l
Up to 112 I/Os
Up to 16 Ext. ITs 2 x SPI
2-channel 12-bit DAC
2 x Watchdog(independent & window)
6 x 16-bit Timer
AR
M®
P(m
a
2 x I2C
Modem Control
1 x USART/LINSmartcard/IrDaModem Control
1 x SPI1 x 12-bit ADC / 1Msps
up to 21 channels
Temperature Sensor
STM32 Seminar November 2010
More flexibility with STM32 XL Density
Doubles available Flash up to 1 Mbyte with up to 96 Kbytes of SRAMp y
New devices in both Access and Performance lines
Additional extra featuresAdditional extra featuresSix additional 16-bit timersMemory Protection Unit (MPU)
News features benefit in applicationTwo 512-Kbyte banks of Flash for safe in-application software upgradingapplication software upgradingAdditional timers for motor control or factory automation applicationsMPU to protect specific code or data
STM32 Seminar November 2010
STM32F10x XL Density
• up to 1MB Flash
t 96KB RAM
CORTEXTM-M3 CPU + MPU
72 MHzPower Supply
Reg 1.8Vash
I/F 784KB – 1MB Flash Memory• up to 96KB RAM
• MPU (transparent for the user if not
72 MHz
JTAG/SW Debug
POR/PDR/PVD
peed
Bus
ax 3
6/ 7
2MH
z)
XTAL oscillators32KHz + 4~16MHz
Int. RC
80kB-96KB SRAM
Fla Flash Memory
84B Backup Datafor the user if not used)
• 6 additional timers
FSMCSRAM/ NOR/NAND/CF/ LCD parallel interface
g
DMA
Nested vect IT Ctrl
1 x Systick Timer
M ®
Lite
Hi-S
ix /
Arb
iter (
ma
ETMInt. RC
oscillators40KHz + 8MHz
PLL
p
• RWW Flash1 x USB 2.0FS
DMAup to 12 Channels
Bridge
Bridge
AR
MM
atri RTC / AWU
ARM® Peripheral Bus(max 36MHz)
SDIOSD/SDIO/MMC/CE-ATA
Clock Control
iphe
ral B
us72
MH
z)
4 x USART/LINUp to 112 I/Os
Up to 16 Ext. ITs
1 x CAN 2.0B2 x 16-bit PWM Synchronized AC Timer
2 x SPI / I²S
g
2 x Watchdog(independent & window)
10 x 16-bit Timer
AR
M®
Peri
(max
7
2 x I2C
Smartcard / IrDaModem Control
Up to 112 I/Os
1 x USART/LINSmartcard/IrDa
1 x SPI
2-channel 12-bit DAC
3 x 12-bit ADC / 1Mspsup to 21 channels
T t S
STM32 Seminar November 2010
2 x I2CModem Control Temperature Sensor
STM32 Value line 256K-512KBytes
Core and operating conditionsARM® Cortex™ M3 1 25
CORTEXTM-M3 CPU
24 MHzPower Supply
Reg 1.8VPOR/PDR/PVDFl
ash
I/F 256KB-512kBFlash Memory
ARM® Cortex™-M3 1.25 DMIPS/MHz up to 24 MHz 2.0 V to 3.6 V range -40 to +105 °C JTAG/SW Debug
Nested Vect IT Ctrl -Spe
ed 3
6us
(max
24M
Hz)
XTAL oscillators32KHz + 4~25MHz
Int. RC oscillators
24KB-32kB SRAM
84B Backup Data
Rich connectivity11 communications peripherals
FSMC
SRAM/ NOR/ LCD parallel interface
DMAt 12 Ch l
Nested Vect IT Ctrl
1 x Systick Timer
AR
M ®
Lite
Hi-
Mat
rix /
Arb
iter
RTC / AWU
oscillators40KHz + 8MHz
PLL
Clock ControlFSMC
SRAM, NOR, memories support. LCD Parallel interface 8/16-bitIntel 8080 and Motorola 68K
up to 12 Channels
Bridge
Bridge
A
ARM® Peripheral Bus
(max 24MHz)
Clock Control
1 x 16-bit PWM
Enhanced control16-bit motor control timer10x 16-bit PWM timers
Perip
hera
l Bus
ax 2
4MH
z)
4 x USART/LINSmartcard / IrDa51/80/112 I/Os
Up to 16 Ext. ITs
2 x12-bit DAC
2 x Watchdog(independent & window)
10 x 16-bit Timer 1 x CECSynchronized AC Timer
LQFP64, LQFP100, LQFP144 AR
M®
P(m
a
2 x I2C
Modem Control
1 x USART/LINSmartcard/IrDaModem Control
1 x SPI1 x 12-bit ADCup to 16 channels
Temperature Sensor
2 x SPI
STM32 Seminar November 2010
STM32 Value line key features
High-performance coreARM® Cortex™-M3 zero wait state 1.25 DMIPS/MHz
up to 30 DMIPS at 24 MHz max
Essential features for appliances, consumer and industrialSeven PWM 16-bit timers including motor control timer, fast 1.2 µs 12-bit ADC & dual 12-bit DAC Consumer Electronic Control (CEC) hardware functionFl ibl St ti M C t ll (FSMC) dd i SRAM PSRAM NOR t ls B
ly Flexible Static Memory Controller (FSMC) addressing SRAM, PSRAM, NOR external
memories LCD parallel interface supportD
evic
es>=
256
KB
Flas
h on
ly
From 16-Kbyte up to 512-Kbyte Flash
From 48-pin to 144-pin packagesFrom 48-pin to 144-pin packages
Under $1 most accessible STM32From $0 85 (resale 10 Ku) for 16-Kbyte devices in LQFP48 package
STM32 Seminar November 2010
From $0.85 (resale 10 Ku) for 16-Kbyte devices in LQFP48 package
STM32 in action (alarm control panel)
To phone line, alarm sensors and I/Os
Serial coms and I/Os
5 UARTs, 3 SPI, 2 I²C5 timers, up to 112 I/Os
3 ADC, 21 channels2 DACs
FSMC
2 DACs
Parallel interface to
I²S
Interface to audio DAC for hi fi di lit
FSMC
graphic module
SDIO
hi-fi audio quality
Audio for the userVoice and music QVGA O
SD Wi-Fi cardto home network
SD card for software upgrade
LCD
STM32 Seminar November 2010
STM32 W lk Th h thSTM32 Walk-Through the PeripheralsPeripherals
Memory Mapping and Boot Modes - MD
Boot modesD di th B t fi ti E b dd d Fl h
Addressable memory space of 4 GBytesRAM : up to 96 kBytesFLASH : up to 1024 kBytes
BOOT Mode 0xE010 0000
0xFFFF FFFF
Depending on the Boot configuration, Embedded FlashMemory, System Memory or Embedded SRAM Memoryis aliased at @0x00
FLASH : up to 1024 kBytes
Cortex-M30xE00F FFFF
Reserved
Selection Pins Boot Mode Aliasing
BOOT1 BOOT0
x 0User Flash User Flash is selected as
boot spaceReserved
O ti B t0x1FFF F80F
Cortex-M3 internal
peripherals0xE000 0000
0 1 SystemMemory SystemMemory is selected as boot space
1 1 Embedded SRAM
Embedded SRAM is selected as boot space
Reserved
0x1FFF F000
0x1FFF F7FFSystemMemory
Reserved
Option Bytes 0x1FFF F800
Peripherals0x4000 0000Reserved
0x0800 0000
0x0801 FFFF
Flash
Reserved
SystemMemory: contains the Bootloader used to re-program the FLASH through USART1.For more details refer to AN2606 & UM0462A PC Windows Demonstrator is available as well.
CODE
SRAM
0x0000 0000
0x2000 0000Reserved
Bit-Band region
Boot from SRAM :In the application initialization code you have to Relocatethe Vector Table in SRAM using the NVIC Exception Tableand Offset register
STM32 Seminar November 2010
System Architecture - MDMultiply possibilities of bus accesses to SRAM, Flash, Peripherals, DMA
BusMatrix added to Harvard architecture allows parallel access
Effi i t DMA d R id d t flEfficient DMA and Rapid data flowDirect path to SRAM through arbiter, guarantees alternating access
Harvard architecture + BusMatrix allows Flash execution in parallel with DMA transfer
Increase Peripherals Speed for better performanceIncrease Peripherals Speed for better performanceDual Advanced Peripheral buses (APB) architecture w/ High Speed APB (APB2) up to 72MHz and Low Speed APB (APB1) up to 36MHz
Allows to optimize use of peripherals (18MHz SPI, 4.5Mbps USART, 72MHz PWM Timer, 18MHz toggling I/Os)
Bu
Bu
System
D-bus
I-bus
CORTEX-M3Master 1
CORTEX-M3Master 1
SRAMSRAM
FLASHFLASH
Flas
h I/F
Flas
h I/F
usMatrix
usMatrix
System
GP-DMAGP-DMA
SRAMSlaveSRAMSlave
AHB-APB2AHB-APB2AHB
GPIOA,B,C,D,E - AFIO –USART1- SPI1 - ADC1,2 -
TIM1 - EXTI
GPIOA,B,C,D,E - AFIO –USART1- SPI1 - ADC1,2 -
TIM1 - EXTIAPB2
Buses are not overloaded with data movementxxGP DMA
Master 2GP DMAMaster 2
AHB APB2AHB APB2AHB-APB1AHB-APB1
AHB
Bridges
APB1
Arbiter
USART2,3 - SPI2 - I2C1,2 –TIM2,3,4 - IWDG– WWDG –USB – CAN – BKP – PWR –
USART2,3 - SPI2 - I2C1,2 –TIM2,3,4 - IWDG– WWDG –USB – CAN – BKP – PWR –
STM32 Seminar November 2010
Buses are not overloaded with data movement tasks
Embedded FLASHEmbedded FLASH
STM32 Seminar November 2010
Flash Features OverviewFlash Features:
Up to 1024KBytes 1 2 KB t P i1 or 2 KByte Page sizeEndurance: 10k cyclesMemory organization:
Main memory blockInformation block
Access time: 35nsHalfword (16-bit) program time: 52.5 μs (Typ)Page / Mass Erase Time: 20ms
Flash interface (FLITF) Features:Flash interface (FLITF) Features:Read Interface with pre-fetch bufferOption Bytes loaderFlash program/Erase operationsTypes of Protection:
Readout Protection
STM32 Seminar November 2010
Write Protection
Flash Memory AcceleratorMission:Mission: Support 72 MHz72 MHz operation directly from Flash memory64-bits wide Flash with Prefetch (2 × 64bits buffers)( )
Memory Accelerator
tsBits
Instructions-BUS
ARBITER ARBITER ** bi
tsbi
ts
FLASH MEMO
RYbits
…
64 b
it
32 bits 16 bits16 bits
32 –
16 –
16
Thum
b-2
BUS **
64 b
64 b RY
64 …
bits
32 bitsThumb-2
16 bitsThumb-2
16 bitsThumb
32 b
itsTh
umb-
2
CORTEX-
Data/Debug-
ARRAY64 b
32 b
itsTh
umb-
2
CORTEX-M3
CPU gBUS 32 bits
Data16-bitData
8 bitData
STM32 Seminar November 2010* The data (constant or literals ) are provided with the highest priority using the D-Bus.
Cyclic Redundancy Check (CRC)y y ( )
STM32 Seminar November 2010
CRC FeaturesCRC-based techniques are used to verify data transmission or storage integrity
Uses CRC-32 (Ethernet) polynomial: 0x4C11DB7X32+ X26+ X23 + X22 + X16+ X12 + X11+ X10 + X8 + X7 + X5 + X4 + X2 + X + 1
AHB Bus
Single input/output 32-bit data register
CRC computation done in 4 AHB clock cycles
Data register (Output)
32-bit (read access)p y
(HCLK)
General-purpose 8-bit register (can be used for
CRC computation (polynomial: 0x4C11DB7)
D t i t (I t)
32-bit (write access)
p p g (temporary storage)
Data register (Input)
STM32 Seminar November 2010
Di t M A (DMA)Direct Memory Access (DMA)
STM32 Seminar November 2010
DMA Features7/12 independently configurable channels: hardware requests or software trigger on each channel.
Software programmable priorities: Very high, High, Medium or Low. (Hardware priority in case of equality).
Programmable and Independent source and destination transfer data size: Byte, Halfword or Word.
3 event flags for each channel: DMA Half Transfer DMA Transfer complete3 event flags for each channel: DMA Half Transfer, DMA Transfer complete and DMA Transfer Error.
Memory-to-memory, peripheral-to-memory, memory-to-peripheral transfers y y, p p y, y p pand peripheral-to-peripheral transfers
Faulty channel is automatically hardware disabled in case of bus access error
Programmable number of data to be transferred: up to 65535.
STM32 Seminar November 2010
Support for circular buffer management
DMA Request MappingThe DMA controller provides access to 7 channels
USART1_TX
ADC1
TIM2_CC3 TIM4_CC1
USART3_TX
TIM1_CC1
TIM2_UP TIM3_CC3
SPI1 RX
USART3_RX
TIM1_CC2
SPI1_TX
TIM3_CC4
TIM3_UPSPI2 RX I2C2 TX
TIM1_CC4
TIM1_CCU
TIM1_TRIG
TIM4_CC2 USART1_RXTIM1_UP
SPI2_TX
I2C2_RX
TIM2_CC1
TIM4_CC3
USART2_RX
TIM1_CC3TIM3_CC1
TIM3 TRIG
USART2_TX
TIM2_CC2 TIM2_CC4
TIM4_UP I2C1_RX
OR OR OR OR OR OR OR
SPI1_RX _ I2C2_TXI2C1_TX TIM3_TRIG
SW TRIGGER SW TRIGGER SW TRIGGER SW TRIGGER SW TRIGGER SW TRIGGER SW TRIGGER
DM
A
Channel1 Channel2 Channel3 Channel4 Channel5 Channel6 Channel7
D
DMA REQUEST
High Priority Request
Low Priority Request
STM32 Seminar November 2010
DMA Latency: 1 transferRequest 1 Request 2
1 cycle 1 cycle 5 cycles 1 cycle
Request1 sample & arbitration phase
Bus accessAddress computation Acknowledgement phase Request2 sample & arbitration phase
8 cycles for each request (source and destination on AHB)
If source or destination is a peripheral on APB, Bus access will include more cycles due to the AHB/APB bridge latency and APB transfer duration, depending on the AHB/APB ratio.
APB AHB 1 1 2 l t t l 10 lAPB:AHB = 1:1 -> + 2 cycles => total = 10 cycles
APB:AHB = 1:2 -> + 3-4 cycles => total = 11-12 cycles
If the CPU is running, the DMA access (AHB or APB) may be delayed by 1 bus cycle on each of the buses
For RAM access, any read after write access takes 1 extra cycle, y y
Example: APB:AHB = 1:1 ,DMA “APB->AHB transfer” and CPU is only accessing RAM (no APB access)
The maximum latency between 2 DMA accesses will be 12 cycles
STM32 Seminar November 2010
Reset and Clock Control (RCC)Reset and Clock Control (RCC)
STM32 Seminar November 2010
RESET Sources
System RESET R t ll i t t RCC
VDD
Resets all registers except some RCC registers and BKP domainSources
Low level on the NRST pin
Filter
RPU
PULSE
SYSTEM RESETNRST
WWDG RESETIWDG RESET
External RESET
p(External Reset)WWDG end of count conditionIWDG end of count conditionA soft are reset (thro gh NVIC)
PULSEGENERATOR
(min 20µs)
IWDG RESETSoftware RESETPower RESETLow power management RESET
A software reset (through NVIC)Low power management Reset
P RESET B k d i RESETPower RESETResets all registers except BKP domainSources
Power On/Power down Reset
Backup domain RESETResets all BKP domainSources
Setting BDRST bit in RCC BDCRPower On/Power down Reset (POR/PDR)When exiting STANDBY mode
Setting BDRST bit in RCC BDCR registerVDD or VBAT power on, if both supplies have previously been powered off
STM32 Seminar November 2010
powered off.
On-Chip OscillatorsMultiple clock sources for full flexibility in RUN/Low Power modes
HSE (High Speed External oscillator): 4MHz to 16MHz main osc which can be multiplied by the PLL t id id f f ito provide a wide range of frequencies
Can be bypassed with external clock
HSI (High Speed Internal RC): factory trimmed internal RC oscillator 8MHz +/- 1% over 0-70°C temp range
Feeds System clock after reset or exit from STOP mode for fast startup (startup time : 2us max)( p )
Backup clock in case HSE osc is failing
Note: When the HSI is used as a PLL clock input the maximum systemNote: When the HSI is used as a PLL clock input, the maximum system clock frequency that can be achieved is 64 MHz.
LSI (Low Speed Internal RC): 40KHz internal RC for IWDG and optionally for the RTC used for Auto Wake-Up (AWU) from STOP/STANDBY modeWake Up (AWU) from STOP/STANDBY mode
LSE (Low Speed External oscillator): 32.768kHz osc provides a precise time base with very low power consumption (max 1µA). Optionally drives the RTC for Auto Wake-Up (AWU) from STOP/STANDBY mode.
STM32 Seminar November 2010
Can be bypassed with external clock
Clock Scheme System Clock (SYSCLK) sources
HSI HSE
RTC Clock (RTCCLK) sourcesLSELSIHSE clock divided by 128
USB Clock (USBCLK) provided from the internal PLL
Clock-out capability on the MCO PLL
Configurable dividers provides AHB, APB1/2, ADC and TIM clocks
HSE clock divided by 128
Clock Security System (CSS) to backup clock in case of HSE clock failure (HSI feeds the system clock)
p ypin (PA.08) / max 50MHz
AHB, APB1/2, ADC and TIM clocks failure (HSI feeds the system clock)Enabled by SW w/ interrupt capability linked to Cortex NMI
PCLK1 up to 36MHz
HCLK up to 72MHz
HSI RC8MHz
TIMxCLK
TIM2,3,4
APB1 Prescaler/1,2,4,8,16
AHB Prescaler/1,2…512
If (APB1 pres =1) x1
Else x2
to 36MHz
PCLK2 up
HSE OscOSC_OUT
OSC_IN
4 -16 MHz up to 72
MHz
SYSCLKx2...x16 PLL
PLLCLK
/2
/2
TIM1CLK APB2
Prescaler/1,2,4,8,16
If (APB2 pres =1) x1
Else x2
PCLK2 up to 72MHz
CSSSYSCLK
HSIHSE
PLLCLK
MCO
/2/128
ADC Prescaler
/2,4,6,8ADCCLK
USB Prescaler
/1,1.5
USBCLK 48MHz
32.768KHz LSE OSc
OSC32_IN
OSC32_OUT
~40KHz
RTCCLK
STM32 Seminar November 2010
LSI RC40KHz
IWDGCLK
G l P d Alt tGeneral Purpose and Alternate Function I/O (GPIO and AFIO)
STM32 Seminar November 201062
GPIO FeaturesUp to 80 multifunction bi-directional I/O ports available: 80% IO ratio
Standard I/Os 5V tolerant
The GPIOs can sink 25mA ( total currents sunk is 150mA )
18 MHz Toggling
Configurable Output Speed up to 50 MHzConfigurable Output Speed up to 50 MHz
Up to 16 Analog Inputs
Alternate Functions pins (like USARTx, TIMx, I2Cx, SPIx, CAN, USB…)
Up to 80 GPIOs can be set-up as external interrupt (up to 16 lines at time)
One I/O can be used as Wake-Up from STANDBY (PA.00)
One I/O can be set-up as Tamper Pin (PC.13)
All Standard I/Os are shared in 5 ports (GPIOA..GPIOE)
Atomic Bit Set and Bit Reset using BSRR and BRR registersAtomic Bit Set and Bit Reset using BSRR and BRR registers
Locking mechanism to avoid spurious write in the IO registersWhen the LOCK sequence has been applied on a port bit, it is no longer possible to modify the configuration of the port bit until the next reset (no write access to the CRL and CRH
STM32 Seminar November 2010
the configuration of the port bit until the next reset (no write access to the CRL and CRH registers corresponding bit).
GPIO Configuration ModesAnalog Input
To On-chip Peripherals
Configuration Mode CNF1 CNF0 MOD1 MOD0
Analog Input 0 0VDD
Reg
iste
r
Alternate Function Input
ON OFFRead
Input Floating (Reset State)
0 1
Input Pull-Up 1 0
00
ON/OFF
Pull
-UP
nput
Dat
aR
TTL Schmitt
Trigger
VDD or VDD_FT(1)0
Read
Input Pull-Down 1 1
Output Push-Pull
0 0 ON/OFF Pull
-Dow
n
eset
rs
InR
egis
ter
I/O p
in
VDD
Input Driver
Output Driver
Push-Pull
01: 10 MHz10: 2 MHz11: 50 MHz
OutputOpen-Drain
0 1
AF Push-Pull 1 0
P
VSS
BitS
et/R
eR
egis
ter
putD
ata
R
Push-Pull orO D i
OUTPUT CONTROL
VSSAFOpen-Drain
1 1
Write
B
OutRead / Write
Alternate Function OutputFrom On-chip Peripherals
Open Drain
VSS(1) VDD for standard I/Os and VDD_FT is a
potential specific to five-volt tolerant I/Os and different from VDD.
or disabled
STM32 Seminar November 2010
Real-Time Clock (RTC)Real Time Clock (RTC)
STM32 Seminar November 2010
RTC FeaturesClock sources
32.768 kHz dedicated oscillator (LSE)
Low frequency (40kHz), low power internal RC(LSI)
HSE OSC
LSI RC
HSE divided by 128
3 Event/Interrupt sourcesSecond
Overflow
1/12
8
LSE OSC or EXT ClockOverflow
Alarm (also connected to EXTI Line 17 for Auto Wake-Up from STOP)
Register protection against unwanted write operations=
RTC Prescaler
RTC AlarmRTCSEL
[1:0]
RTC core & clock configuration in Backup domainIndependent VBAT voltage supply
Reset only by Backup domain reset
RTC config kept after reset or wake up from STANDBY
RTC Counter RTC Divider
fRTC
Backup DomainRTC config kept after reset or wake-up from STANDBY
Calibration CapabilityRTC clock divided by 64 can be output on Tamper pin for calibration
RTC Control Register (CR)
Backup Domain
Then the clock can be adjusted from 0 to to 121ppm by a step of 1ppm
Possibility to output the Alarm pulse or Second pulse on Tamper pin (even when the device is in STANDBY mode)
Alarm IT Overflow IT Second IT
STM32 Seminar November 2010
Window Watchdog (WWDG)g ( )
STM32 Seminar November 2010
WWDG featuresConfigurable time-window, can be programmed to detect abnormally late or early application behavior
Conditional reset WWDG_CFRWWDG ResetConditional reset
Reset (if watchdog activated) when the down counter value becomes less than 40h (T6=0)
Reset (if watchdog activated) if the down counter is reloaded id h i i d
CMP
W0W1W2W3W4W5W6-
comparator= 1 when
T6:0 > W6:0
eset
outside the time-window
To prevent WWDG reset: write T[6:0] bits (with T6 equal to 1) at regular intervals while the counter value is lower than the time-window value (W[6:0])
T0T1T2T3T4T5T6WDGA
WWDG_CR 6-Bit Down Counter
Write WWDG_CR
( [ ])
Early Wakeup Interrupt (EWI): occurs whenever the counter reaches 40h can be used to reload the down counter
T[6:0] CNT down counter
PRESCALER (WDGTB)
PCLK1 (up to 36MHz)
WWDG reset flag (in RCC_CSR) to inform when a WWDG reset occurs
Min-max timeout value @36MHz (PCLK1): 113μs / 58.25ms
W[6:0]
3Fh
58.25ms
Best suited to applications which require the watchdog to react within an accurate timing window
Refreshnot allowed
RefreshWindow
time
T6 bit
Reset
STM32 Seminar November 2010
Independent Watchdog (IWDG)
STM32 Seminar November 2010
IWDG featuresSelectable HW/SW start through option byteAdvanced security features:
IWDG l k d b it d di t d l d l k (LSI)IWDG clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails
Once enabled the IWDG can’t be disabled (LSI can’t be disabled too)
S f R l d S (k )
PrescalerRegister
Status Register
ReloadRegister
Key Register
1.8V voltage domain
Safe Reload Sequence (key)
IWDG function implemented in the VDD voltage domainthat is still functional in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY)
8-bitPRESCALER
LSI (40KHz)
12-bit reload value
12-bit IWDG
To prevent IWDG reset: write IWDG_KR with AAAAhkey value at regular intervals before the counter reaches 0
IWDG reset flag (in RCC CSR) to inform when a
down counter Reset
VDD voltage domain
IWDG reset flag (in RCC_CSR) to inform when a IWDG reset occurs
Min-max timeout value @40KHz (LSI): 100μs / 26.2s
Best suited to applications which require the watchdog to run as a totally independent
process outside the main application
STM32 Seminar November 2010
Analog-to-Digital Converter (ADC)Analog-to-Digital Converter (ADC)
STM32 Seminar November 2010
ADC Features (1/2)
ADC conversion rate 1 MHz and 12-bit resolution
1µs conversion time at 56 MHz (or any X*14Mhz)µ ( y )
1.17µs conversion time at 72 MHzConversion range: 0 to 3.6 VADC supply requirement: 2 4V to 3 6 VADC supply requirement: 2.4V to 3.6 V
ADC input range: VREF- ≤ VIN ≤ VREF+ (VREF+ and VREF- available only in LQFP100 package)Dual mode (on devices with 2 ADCs): 8 conversion mode
Up to 18 multiplexed channels:
16 external channels16 external channels
2 internal channels: connected to Temperature sensor and internal reference voltage (VREFINT = 1.2V)
Channels conversion groups:Up to 16 channels regular groupUp to 16 channels regular group
Up to 4 channels injected group
Single and continuous conversion modes
STM32 Seminar November 2010
ADC Features (2/2)
Sequencer-based scan mode for up to 16 conversion
External trigger option for both regular and injected conversionExternal trigger option for both regular and injected conversion
Channel by channel programmable sampling time
Discontinuous mode on regular and injected groups
Left or right Data alignment with inbuilt data coherency
Analog Watchdog on high and low thresholds
Interrupt generation on:End of Conversion
End of Injected conversion
Analog watchdog
DMA capability (only on ADC1)
STM32 Seminar November 2010
ADC Block DiagramVREF+
VREF-
VDDA
VSSA ADCCLKADCCLK ADC Prescalers:PCLK2PCLK2
AN
A
GPIOPorts
ADCADC
Up to 4
ADC_IN0
ADC_IN1
.
.I j t d d t i t
Add
DMA RequestDMA Request
ADC Prescalers: Div2, Div4, Div6 and Div8
ALO
G M
UX
Ports
Temp Sensor
VREFINT
Up to 16
Injected Channels
Regular Channels
ADC_IN15
. Injected data registers (4x12bits)
ress/data bus
Regular data register (12bits)
End of injected
TIM1_TRGO
TIM1_CC4
TIM1_TRGO
TIM2 CC1
VREFINT
Start Trigger (injected group)
Analog Watchdog
High Threshold register (12bits)
Analog watchdog event
End of injected conversionEnd of conversion
TIM1 CC1
_CC
TIM3_CC4
TIM4_TRGOJEXTRIG bit
Ext_IT_15JEXTSEL[2:0] bits
Low Threshold register (12bits) AWD EOC JEOC
AWDIE EOCIE JEOCIE
Flags
Interrupt enable bits_
TIM1_CC2
TIM1_CC3
TIM2_CC2
TIM3_TRGO
TIM4_CC4
Ext_IT_11
EXTRIG bit
Start Trigger (regular group)
ADC interrupt to NVIC
STM32 Seminar November 2010
EXTSEL[2:0] bits
Analog sample timeADCCLK, up to 14MHz, taken from PCLK2 through a prescaler (Div2, Div4, Div6 and Div8) , )
Three bits programmable sample time cycles for each channel:g y1.5 cycles
7.5 cycles
13.5 cycles
ADCADC
7.5 cycles
1.5 cycles
Sa
Sa
28.5 cycles
41.5 cycles
55.5 cycles
ADCCLKADCCLKADC Prescalers: Div2, Div4, Div6 and Div8
PCLK2PCLK2
55.5 cycles
41.5 cycles
13.5 cycles
28.5 cycles
ample Tim
e Selectio
ample Tim
e Selectio
71.5 cycles
239.5 cycles
55.5 cycles
71.5 cycles
239.5 cycles
onon
SMPx[2:0]
Total conversion = Sample time + 12.5 cycles (fixed time)@ 14MH d S l ti 1 5 l t t l i 1
STM32 Seminar November 2010
@ 14MHz and Sample time=1.5cycle total conversion: 1µs (14 cycles)
Sequencer
Up to 16 conversions with different order, different sampling time d li ibiliand oversampling possibility.
Example: - Conversion of channels: 1, 2, 8, 4, 7, 3 and 11
- Different sampling time.
- Oversampling of channel 7.
Channel1 Channel2 Channel8 Channel4 Channel7 Channel7 Channel7 Channel3 Channel11
13.5 cycles 28.5 cycles7.5 cycles7.5 cycles1.5 cycles 1.5 cycles71.5 cycles
STM32 Seminar November 2010
ADC conversion modes
Four conversion mode are available:Four conversion mode are available:
Start Start
CHx
StopStart
CHx
Start
SingleSingle channelchannelCHx
...
CHn
CHx
...
CHn
Single Single channelchannel
single single conversion modeconversion mode
Single Single channelchannel
continuouscontinuous conversion modeconversion mode
Stop
CHn
MultiMulti--channels (Scan) channels (Scan) MultiMulti--channels channels (Scan)(Scan)continuous conversion modecontinuous conversion modesingle conversion modesingle conversion mode continuous conversion modecontinuous conversion mode
STM32 Seminar November 2010
ADC discontinuous conversion mode
Split channels conversion sequence into sub-sequences
Available for both regular and injected groups:Up to 8 conversion for regular channel
1 conversion for injected channel
Example: - Conversion of channels: 0 1 2 4 5 8 9 11 12 13 14 and 15Example: Conversion of channels: 0, 1, 2, 4, 5, 8, 9, 11, 12, 13, 14 and 15
- Discontinuous mode - Number of channel is 3
1st trigger 2nd trigger 3rd trigger
Channel0 Channel1 Channel2 Channel4 Channel5 Channel8 Channel9 Channel11 Channel12
gg gg gg
h
Channel13 Channel14 Channel15
4th trigger
End of Conversion
Channel0 Channel1 Channel2
5th trigger
…Note:Note: Do not use discontinuous mode for both
regular and injected together. It can be
used only for one group channel
STM32 Seminar November 2010
ADC Analog Watchdogs
12-bit programmable analog watchdog low and high thresholds
Enabled on one, or all converted channels: one regular or/and injected channel, all injected or/and regular channels.
Interrupt generation on low or high thresholds detectionp g g
Analog Watchdog
ADC_IN0
ADC_IN1
. AWD
Status RegisterLow ThresholdLow Threshold
Temp Sensor
ADC_IN15
.
.
High ThresholdHigh Threshold
VREFINT
STM32 Seminar November 2010
DMADMA available only on ADC1
DMA request generated on each ADC1 end of regular channelDMA request generated on each ADC1 end of regular channel conversion (Not in injected channels)
Channel0 Channel1 Channel2 Channel3 Channel4 Channel5 Channel6 Channel7 Channel8
DMA Request
DMA Request
DMA Request
DMA Request
DMA Request
DMA Request
DMA Request
DMA Request
DMA Request
Example: - Conversion of regular channels: 0, 1, 2, 3, 4, 5, 6, 7 and
8Channel8 conversion result
Channel7 conversion result
ConvertedValue_Tab[9]
- Converte data stored in ConvertedValue_Tab[9]
- DMA transfer enabled (destination address auto
incremented)
Channel7 conversion result
Channel6 conversion result
Channel5 conversion result
Channel4 conversion result
Channel3 conversion result
ADC1 DR registerADC1 DR register....
Channel3 conversion result
Channel2 conversion result
Channel1 conversion result
Channel0 conversion result
..
Note: EOC flag cleared at end of regular channels conversion due
to DMA access to ADC1 DR register
STM32 Seminar November 2010
ADC dual modes
Available in devices with two ADCs: ADC1 master and ADC2 slave
ADC1 and ADC2 triggers are synchronized internally for regularand injected channels conversion
8 ADC dual modesGPIOPorts
Temp Sensor
VR
EFINT
ADC_IN0
…
ADC_IN1ADC_IN15
…
Up to 4 injected channels Up to 16 regular channels
ANALOG MUX
ADC1Analog
ADC2Analog
Digital Master Digital Slave
External event synchronizationExternal event (Regular group)
External event (Injected group) Data registerg ta aste g ta S a e
EOC/JEOC
STM32 Seminar November 2010
Advanced Control And General Purpose Timers
STM32 Seminar November 2010
Features overviewGeneral Purpose Feature16-bit Counter
Auto ReloadUp down and centered counting
ITR 1 Trigger/ClockTrigger
Clock
ITR 2
ETR
Up, down and centered counting modes
4x 16 High resolution Capture Compare channelsProgrammable direction of the channel: input/outputOutput Compare: Toggle, PWM
ControllerTrigger OutputITR 3
ITR 4
Input CapturePWM Input Capture
SynchronizationUp to 8 IT/DMA RequestsMotor Control Specific Feature
16-Bit Prescaler
Auto Reload REG/ 16 Bit C tMotor Control Specific Feature
OC Signal Management6 Complementary outputs Dead-time management Repetition Unit
CH1CH1N
+/- 16-Bit Counter
CH1pEncoder InterfaceHall sensor InterfaceEmbedded Safety features
Break sources: BKIN pin/ CSS
CH1N
CH2CH2N
CH3
Capture CompareCapture Compare
Capture CompareCapture Compare
CH1
CH2
CH3 Lockable unit configuration
CH3CH3NCH4
BKIN
CH4
STM32 Seminar November 2010
Counter ModesThere are three counter modes:
Up counting modeD ti dDown counting modeCenter-aligned mode
When using the Repetion Counter (case of TIM1 only)
Center Aligned Up counting Down counting
RCR = 0
UEV
RCR = 2RCR = 2
UEV
STM32 Seminar November 2010105
Counter Clock SelectionClock can be selected out of 8 sources
Internal clock TIMxCLK provided by the RCCInternal trigger input 1 to 4:
ITR1 / ITR2 / ITR3 / ITR4
TIMxCLK Trigger Controller
Using one timer as prescaler for another timer
External Capture Compare pinsPin 1: TI1FP1 or TI1F ED TRGOITR1
Polarity selection & Edge Detector & Prescaler & FilterETR
Pin 1: TI1FP1 or TI1F_ED Pin 2: TI2FP2
External pin ETREnable/Disable bit
TRGOITR2ITR3
ITR4TI1F_ED
Controller
Programable polarity4 Bits External Trigger FilterExternal Trigger Prescaler:
TI1FP1
TI2FP2
Prescaler offDivision by 2Division by 4Division by 8
STM32 Seminar November 2010
Division by 8
Serial Peripheral Interface (SPI)
STM32 Seminar November 2010
SPI Features (1/2)
Two SPIs: SPI1 on high speed APB2 and SPI2 on low speed APB1
Full duplex synchronous transfers on 3 lines
Simplex synchronous transfers on 2 lines with or without a bi-directional data line
Programmable data frame size :8- or 16-bit transfer frame format selection
Programmable data order with MSB-first or LSB-first shifting
Master or slave operationMaster or slave operation
Programmable bit rate: up to 18 MHz in Master/Slave mode
NSS management by hardware or software for both master and slave: Dynamic change of Master/Slave operations
STM32 Seminar November 2010
SPI Features (2/2)
Programmable clock polarity and phase
Dedicated transmission and reception flags (Tx buffer Empty and Rx buffer Not Empty) with interrupt capabilityEmpty) with interrupt capability
SPI bus busy status flag
Master mode fault and overrun flags with interrupt capability
Hardware CRC feature for reliable communication
Support for DMA
STM32 Seminar November 2010
Data Frame Format
Data frame format :Data frame format :
Programmable data frame size :8- or 16-bit transfer frame format selection
Programmable data order with MSB-first or LSB-first shifting
M t88--bit longbit long
MSB firstMSB first0xD70xD7
MasterSCK
MISO
MOSI
ggLSB firstLSB first0xD70xD7
MOSI
NSS
1616--bit long bit long MSB firstMSB first
VDD
0xD7390xD739
LSB firstLSB first0xD7390xD739
STM32 Seminar November 2010
Full Duplex Communication
SPI t F ll d l d T O l i ti dSPI supports Full duplex and Tx-Only communication mode :
Full-duplex, three-wire synchronous transfer
SlaveSCK
MasterSCK
MISO
MOSI
NSS
MISO
MOSI
NSS
VDD
SS
Full DuplexFull Duplex
STM32 Seminar November 2010
Simplex Communication
SPI supports simplex communication mode:SPI supports simplex communication mode:
Bidirectional: 1 Clock and 1 bi-directional data wire (One bit direction transfer control)Rx-Only: 1 Clock and 1 unidirectional data wire
Tx-Only
SlaveSCK
MISO
MasterSCK
MISO
SlaveSCK
MISO
MasterSCK
MISO
MOSI
NSS
MOSI
NSS
VDD
MOSI
NSS
MOSI
NSS
VDD
Rx Only Rx Only (Slave)(Slave)BiBi--directionaldirectional
STM32 Seminar November 2010
NSS Hardware & Software Management
HardwareHardware NSSNSS Software NSSSoftware NSS
Slave SlaveBoth Master and Slave NSS
i ld b d f th
SCK MISOMOSINSS SCKMISOMOSINSS
pins could be used for other
purpose
VDD
Provides the possibility of
dynamic change of
Master/Slave operations: NoSCK MISOMOSINSS SCK MISOMOSINSS Master/Slave operations: No
hardware limitation to switch
from master to slave or slave
t t i th
Master Master
to master in the same
application
STM32 Seminar November 2010
Multi Master: SS output Management
Slave SlaveEnable SS output
biliEach device can be a unique
SCK MISOMOSINSS SCKMISOMOSINSS
capability master by enabling its NSS as
output and driving it low: all
other devices became slaves.
Rx-only mode
N d f t l GPIOSCK MISOMOSINSS SCK MISOMOSINSS No need for external GPIO
pin to drive slaves NSS pins
Master Slave
STM32 Seminar November 2010
Inter Integrated Circuit (I2C)
STM32 Seminar November 2010
I2C Features (1/2)Multi Master and slave capability
Controls all I²C bus specific sequencing, protocol, arbitration and timingp q g p g
Standard and fast I²C mode (up to 400kHz)
7-bit and 10-bit addressing modes
Dual Addressing Capability to acknowledge 2 slave addresses
Status flags:
Transmitter/Receiver mode flagTransmitter/Receiver mode flag
Byte transfer finished flag
I2C busy flag
Configurable PEC (Packet Error Checking) Generation or Verification:
PEC value can be transmitted as last byte in Tx mode
PEC error checking for last received bytePEC error checking for last received byte
SMBus 2.0 Compatibility
PMBus Compatibility
STM32 Seminar November 2010
Dual Addressing Mode
I2C supports dual addressing capability to acknowledge 2 slave addresses
SlaveMaster
VDD
Slave
SDA
SCL
Master
SDA
SCL
Slaveaddress
1
SlaveSCLSCLaddress
2
STM32 Seminar November 2010
Universal Synchronous Asynchronous Receiver Transmitter y
(USART)
STM32 Seminar November 2010
USART Features (1/2)Three USART: USART1 High speed APB2 and USART2,3 on Low speed APB1
Data can be 8 or 9 bits
Even, odd or no-parity bit generation and detectionUp to 4 5 Mbps0.5, 1, 1.5 or 2 stop bit generation
Programmable baud rate generatorInteger part (12 bits)
Up to 4.5 Mbps
Integer part (12 bits)
Fractional part (4 bits)
Support hardware flow control (CTS and RTS)pp ( )
Dedicated transmission and reception flags (TxE and RxNE) with interrupt capability
S t f DMASupport for DMAReceive DMA request
Transmit DMA request
STM32 Seminar November 2010
q
Synchronous Mode
USART supports Full duplex synchronous communication modeF ll d ple three ire s nchrono s transferFull-duplex, three-wire synchronous transferUSART Master mode onlyProgrammable clock polarity (CPOL) and phase (CPHA)Programmable Last Bit Clock generationTransmitter Clock output (SCLK)
SlaveSCK
MISO
MasterSCLK
Rx
MOSI
NSS
Tx
USART SPI
Full DuplexFull Duplex
STM32 Seminar November 2010
IrDA SIR Encoder Decoder
USART supports the IrDA SpecificationsHalf-duplex, NRZ modulation,Max bit rate 115200 bps3/16 bit duration for normal mode
USARTTx/ SW_RxSIR Transmit
Encoder
USART Tx
IrDA OUT
SIR Receive
HalfHalf DuplexDuplex
Decoder IrDA IN
STM32 Seminar November 2010
HalfHalf DuplexDuplex
Smart Card modeUSART supports Smart Card Emulation ISO 7816-3
Half-Duplex, Clock Output (SCLK)Half Duplex, Clock Output (SCLK)9Bits data, 0.5 Stop Bit in receive, 1.5 Stop Bits in transmitParity Error Generation with NACK transmissionP bl G d Ti (d t i )Programmable Guard Time (data processing)Programmable Clock Prescaler to guarantee a wide range clock input
USARTTx
SCLK
STM32 Seminar November 2010
Single Wire Half Duplex mode
USART supports Half duplex synchronousUSART supports Half duplex synchronouscommunication mode
Only Tx pin is used (Rx is no longer used)
USART2USART1
VDD
Ω
Used to follow a single wire Half duplex protocol.
USART2
Tx
USART1
Tx
R =
10
KHalfHalf DuplexDuplex
STM32 Seminar November 2010
Controller Area Network (bxCAN)Controller Area Network (bxCAN)
STM32 Seminar November 2010
CAN Features (1/2)Main features:
Supports CAN protocol version 2.0 A, B Active
Bit rates up to 1Mbit/sBit rates up to 1Mbit/s
Support the time Triggered Communication option
TransmissionThree transmit mailboxes
Configurable transmit priority
Time Stamp on SOF transmission
ReceptionTwo receive FIFOs with three stages
14 scalable filter banksIdentifier list features
Configurable FIFO overrun
Time Stamp on SOF receptionp p
STM32 Seminar November 2010
Universal Serial Bus interface(USB D i )(USB Device)
STM32 Seminar November 2010
USB Features
Full speed USB 2 0 transfer (certified on USB org)Full speed USB 2.0 transfer (certified on USB.org).
Configurable endpoints transfer mode type: control, bulk, interrupt and Isochronous.
Configurable number of endpoints: up to 8 bidirectional endpoints and 16 mono-directional endpoints.
USB suspend/resume support.
Dedicated SRAM Area (Packet Memory Area) up to 512bytes (shared with bxCAN).
Dynamic buffer allocation according to the user needs.
Special double buffer support for Isochronous and Bulk transfersSpecial double buffer support for Isochronous and Bulk transfers.
STM32 Seminar November 2010
Double Buffering transfer mode
Up to 7 mono-directional Double buffer endpoints (in Bulk or Isochronous transfer types).p p ( yp )
Highest possible transfer rate.
Number of NAKed transactions is limited by the Application elaboration time.
PMA
y pp
Endpointx Buff 1Endpointx Buff 1Endpointx Buff 1
USB IPEndpointx Buff 0
CPUEndpointx Buff 0Endpointx Buff 0
STM32 Seminar November 2010
Peripherals added in Hi h & XL D it STM32High- & XL-Density STM32
STM32F10x High/XL-Densities Main ChangesMemories
SRAM: from 32 KB to 96 KBFLASH: from 256 KB to 1024 KB w/ 2 KB pages size (instead of 1 KB)p g ( )
New IPsSDIOSDIOI2S2 and I2S3 (multiplexed with SPI2 and SPI3)DACFSMC
Added and updated IPsDMA2 w/ 5 channelsADC3SPI3UART 4 and 5, doesn’t support hardware flow control, Smart Card mode (ISO 7816 compliant) and SPI lik i ti bilitSPI-like communication capabilityTIM8 (Advanced Control Timer)TIMER 5 (General Purpose Timer)TIMER 6 and 7 (Basic Timer used to trig the DAC)
STM32 Seminar November 2010
TIMER 6 and 7 (Basic Timer used to trig the DAC)
STM32F10x High-density Series Block DiagramARM 32-bit Cortex-M3 CPUNested Vectored Interrupt Controller (NVIC) w/ 60 maskable IT + 16 prog. priority levelsEmbedded Memories :
Power SupplyReg 1.8V
POR/PDR/PVD
Flas
h I/F Up to 512kB
Flash Memory
CORTEXM3 CPU
72 MHz72 MHz
FLASH: up to 512kBSRAM: up to 64kB
External memory interface FSMC: support NAND, SRAM, NOR, PC Cards and others memory devices2 x DMA w/ 12 channels
XTAL oscillators32KHz + 4~16MHz
Int. RC oscillators40KHz + 8MHzFSMC
SRAM/NOR/NAND/PC C di-S
peed
Bus
er (m
ax 7
2MH
z)(m
ax 7
2MH
z)
Up to 64kB SRAMJTAG/SW Debug
Nested vect IT Ctrl
ETMETM
SDIO: support SD, SDIO, MMC and CE-ATA cardsPower Supply with internal regulator and low power modes :
2V to 3V6 supply4 Low Power Modes with Auto Wake-up
Integrated Power On Reset (POR)/Power Down Reset (PDR) +
PLL
RTC / AWU2 x DMA
12 Channels
84B Backup data
Reset Clock Control
SDIO
PC Cards
AR
M L
ite H
Mat
rix /
Arb
it e
1x Systic Timer
CRCg ( ) ( )Programmable voltage detector (PVD)Backup domain w/ 84B user dataUp to 72 MHz frequency managed & monitored by the Clock Control w/ Clock Security SystemRich set of peripherals & IOs
1x bxCAN 2.0B1x bxCAN 2.0B
1x USB 2.0FS1x USB 2.0FS
Bridge
BridgeARM Peripheral Bus
(max 36MHz)(max 36MHz)
2 x 162 x 16--bit PWM bit PWM Synchronized AC
Timer6 x 16-bit Timer
SDIOSD/SDIO/MMC/
CE-ATA
CRC
Embedded low power RTC with VBAT capabilityDual Watchdog Architecture9 Timers w/ advanced control features (including Cortex SysTick)12 communications Interfaces
Up to 112 I/Os
Up to 16 Ext. ITs
2x SPI/I2S
4x USART/LINSmartcard / IrDaModem Control
Perip
hera
l Bus
max
72M
Hz)
max
72M
Hz)
Timer
Independent Watchdog
Window Watchdog
Up to 112 I/Os (144 pin package) w/ 16 external interrupts/eventUp to 3x12-bits 1Msps ADC w/ up to 21 channels and Embedded temperature sensor w/ +/-1.5° linearity with T°12-bits DAC w/ 2 channels
1x USART/LINSmartcard/IrDa
Modem-Ctrl
1x SPI2x I2C3x3x 12-bit ADC
21 channels / 1Msps
Temp SensorA
RM
(m(m
12-bit DAC 2 channels
STM32 Seminar November 2010174
Flexible Static Memory Controller (FSMC)(FSMC)
STM32 Seminar November 2010
FSMC Features4 Banks to support External memory
FSMC external access frequency is 36MHz when HCLK is at 72MHz
Independent chip select control for each memory bankIndependent chip select control for each memory bank
Independent configuration for each memory bank
Interfaces with static memory-mapped devices including:static random access memory (SRAM)static random access memory (SRAM)
read-only memory (ROM)
NOR Flash memory
PSRAM
Interfaces parallel LCD modules: Intel 8080 and Motorola 6800
Interfaces with Cellular RAM and COSMO RAM, both synchronous and asynchronous random accesses
NAND Flash and 16-bit PC CardsWith ECC hardware up to 8 Kbyte for NAND memory
3 possible interrupt sources (Level, Rising edge and falling edge)
fProgrammable timings to support a wide range of devices
External asynchronous wait controlCode execution only from external SRAM or NOR Flash
STM32 Seminar November 2010
FSMC Block DiagramThe FSMC consists of four main blocks:
The AHB interface (including the IP configuration registers)The NOR Flash/PSRAM controllerThe NOR Flash/PSRAM controllerThe NAND Flash/PC Card controllerThe external devices interface
NOR MemoryController
NOR SignalsFSMC Interrupt to NVIC
ConfigurationShared Signals
FSMCCLK from RCC
AH
B B
us
gRegisters
NAND/PC CardMemory
NAND Signals
yController
PC Card Signals
STM32 Seminar November 2010
FSMC Bank memory mappingFor the FSMC, the external memory is divided into 4 fixed size banks of 4x64 MB each:
Bank 1 can be used to address NOR Flash or PSRAM memory devices.Banks 2 and 3 can be used to address NAND Flash devices.Bank 4 can be used to address a PC Card device.
0x6000 0000Supported Memory Type
Bank 14x64 MB
0x7000 0000
0x6FFF FFFF
NOR / PSRAM / SRAM / CRAM
Bank 2256 MB
0x7000 0000
0x7FFF FFFF
Bank 3256 MB
0x8000 0000 NAND Flash
Bank 4256 MB
0x9000 00000x8FFF FFFF
PC Card
STM32 Seminar November 2010
0x9FFF FFFF
LCD modules interface signals
LCD /RD: The ready signal indicates to the 8080 that valid memory or input data is available on the 8080 data bus.
FSMC_NE[4:1]LCD /CS
LCD /WR: The /WR signal is used for memory write or I/O output control. The data on the data bus is stable while the /WR is active low (/WR = 0).
NOR MemoryController
FSMC_Ax
FSMC_D[15:0]
FSMC_NOE
LCD RS
LCD D[15:0]
LCD /RD
NOR/SRAM Bank
LCD RS: RAM Data/ Register Data Selection
LCD /CS: Chip Select
LCD D[0 15] Bidi ti l d t b
FSMC_NWE
LCD Intel 8080 Controller
LCD /RD
LCD /WR
LCD D[0:15]: Bidirectional data bus
All LCD Signals are controlled by FSMC
FSMC_Ax: where x can be (0..25)
Application Note is available from www.st.com/mcuAN2790: TFT LCD interfacing with the High-density STM32F10xxx FSMC
STM32 Seminar November 2010
Digital to Analog Converter (DAC)Digital-to-Analog Converter (DAC)
STM32 Seminar November 2010
DAC FeaturesTwo DAC converters: one output channel for each one
8-bit or 12-bit monotonic output
Left or right data alignement in 12-bit mode
Synchronized update capability
Noise-wave or Triangular-wave generation
Dual DAC channel independent or simultaneous conversions
DMA capability for each channelDMA capability for each channel
External triggers for conversion
DAC supply requirement: 2.4V to 3.6 Vpp y q
Conversion range: 0 to 3.6 V
DAC outputs range: 0 ≤ DAC_OUTx ≤ VREF+ (VREF+ and VREF- available only in 100 and 144 pins package)
ADC and DAC share the same VREF+
STM32 Seminar November 2010
DAC Channelx Block Diagram
TIM2_TRGO
TIM4_TRGO
TIM5 TRGO
DAC Control Register
SWTRIGx
lect
ion
plitu
de
nera
tion
able
able
TIM5_TRGO
TIM6_TRGO
TIM7_TRGO
TIM8_TRGOExt_IT_9
DMA Request xDMA Request xControl Logic xControl Logic x
Trig
er s
el
Mas
k Am
Wav
e ge
n
Trig
er e
na
DM
A en
a
DMA Request xDMA Request x
TrianglexLFSRxDHRx12 bits
12 bits
VREF+
VDDA DAC OUTxDigital to Analog Converter x
DORx
12 bits
VDDA
VSSA
DAC_OUTxDigital to Analog Converter x
STM32 Seminar November 2010
Triangle Wave GenerationAdd a small-amplitude triangular waveform on a DC or slowly varying signal: used as basic waveform generator for example Calculated triangle value, updated through external trigger, is added to the DAC_DHRx content without overflow to reach the configurable max amplitudeg pUp-Down triangle counter:
Incremented to reach defined max amplitude valueDecremented to return to the initial base value
Triangle max amplitude values are: (2N–1) with N=[1..12]
MAMPx[3:0]: Max amplitude
DAC_DHRx: Base value
STM32 Seminar November 2010
Dual DAC Channel mode
Both DAC channels can be used together: generatedifferential or stereo signals in simultaneous conversion mode
11 DAC dual modes:I d d t t i ith t ith diff tIndependant trigger, without or with, same or different wave generation (LFSR or Triangle)
Si lt ft t tSimultaneous software start
Simultaneous trigger, without or with, same or different wave ti (LFSR T i l )generation (LFSR or Triangle)
STM32 Seminar November 2010
SDIO interfaceSDIO interface
STM32 Seminar November 2010
SDIO Features (1/2)Full compliance with
MMC - Multimedia Card System Specification Version 4.2. Card supportMMC Multimedia Card System Specification Version 4.2. Card support for three different data bus modes: 1-bit (default), 4-bit and 8-bit
Full compatibility with previous versions of Multimedia Cards (forward compatibility)compatibility)
SD Memory Card Specifications Version 2.0SD Memory Card Specifications Version 2.0
SD I/O Card Specification Version 2.0 : card support for two different data bus modes: 1-bit (default) and 4-bit
Full support of the CE-ATA features (full compliance with CE-ATA digital protocol Rev1 1)digital protocol Rev1.1)
Data transfer up to 48 MHz
STM32 Seminar November 2010
SDIO Features (2/2)
Cards Clock Management: Rising and Falling edge, 8-bit prescaler, bypass divider power save (clock output disabled)bypass divider, power save (clock output disabled)
Hardware Flow Control: indicate FIFO contain 2 words or 2 words before full to avoid underrun/overrun .
A 32-bit wide, 32-word FIFO for Transmit and Receive
DMA Transfer Capabilityp y
Data Transfer: Configurable mode (Block or Stream), configurable data block size from1 to 16384 bytes, configurable TimeOut
24 interrupt sources to ease software implementation
CRC Check and generation
SD I/O mode: SD I/O Interrupt, suspend/resume and Read Wait
CE-ATA: CE-ATA end of completion command (CMD61), CE-ATA i t t
STM32 Seminar November 2010
interrupt
SDIO Block Diagram
Interrupts and DMA requests
SDIO_CK
SDIO_CMDThe SDIO consists of two parts:The SDIO adapter block provides all
AHB Interface SDIO Adapter SDIO_D[7:0]
functions specific to the MMC/SD/SD I/O card such as the clockgeneration unit, command and datatransfer.
AHB BusThe AHB interface accesses the SDIO adapter registers, and generates interrupt and DMA request signals
HCLK/2 SDIOCLK (HCLK)
signals.
STM32 Seminar November 2010
SDIO Adapter
The SDIO adapter: bus master that provides an interface to a multimedia
SDIO_CKControlUnit
pcard stack or to a secure digital memory card.
Adapter register block: contains all SDIO t i t
AHB
SDIO_CMD
Adapter Registers
Command Path
SDIO system registers.Control unit: contains the powermanagement functions and the clockdivider for the memory card clock. AHB
Bus SDIO_D[7:0]
FIFO
gData Path
Command path: sends commands to and receives responses from the
d I l t d
HCLK/2 SDIOCLK (HCLK)
cards. Implement command transmission state machineData path: transfers data to and from cards. Implement data transmissionpstate machineData FIFO: contains a 32-bit wide, 32-word deep data buffer, and transmit and receive logic
STM32 Seminar November 2010
and receive logic.
SD/SDIO & MMC CardsThe SDIO has 10 pins to control different kinds of memory cards
Only 6 pins (SDIO_CMD, SDIO_CK, SDIO_D[3:0]) at most for SD cards (SD full size miniSD microSD)size, miniSD, microSD)Only 6 pins (SDIO_CMD, SDIO_CK, SDIO_D[3:0]) at most for SDIO cards (SD full size, miniSD, microSD)10 pins (SDIO CMD, SDIO CK, SDIO D[7:0]) at most for MMC cards (MMC full
SDIOVDD
10 pins (SDIO_CMD, SDIO_CK, SDIO_D[7:0]) at most for MMC cards (MMC full size, RS-MMC, MMC+ and MMCMobile)
SDIOSDIO_CK
SDIO_CMD
SDIO_D0
SDIO D1
81312
7654SDIO_D1
SDIO_D2
SDIO_D3
SDIO_D49
1110
4321
SDIO_D5
SDIO_D6
SDIO_D7
STM32 Seminar November 2010
CE-ATA Devices
1
SDIOSDIO_CK
SDIO_CMD
SDIO D0 A
123456
SDIO_D0
SDIO_D1
SDIO_D2
SDIO_D3
CE-
ATA7
89101112
SDIO_D4
SDIO_D5
SDIO_D6
SDIO_D7
C131415161718_ 18
STM32 Seminar November 2010
SPI InterfaceSPI InterfaceI2S mode
STM32 Seminar November 2010
I2S Features (1/2)
Two I2Ss: Available on SPI2 and SPI3 peripherals.p p
Simplex communication (only transmitter or receiver)
Master or slave operations.
8-bit programmable linear prescaler to reach accurate audio sample frequencies (from 8KHz to 48KHz)
Programmable data format (16-, 24- or 32-bit data formats)
Programmable packet frame (16-bit and 32-bit packet frames).
Underrun flag in slave transmit mode and Overrun flag in receive mode.
16-bit register for transmission and reception16-bit register for transmission and reception.
STM32 Seminar November 2010
I2S Features (2/2)
I2S protocols supported:I2S Philli t d dI2S Phillips standard.
MSB Justified standard (Left Justified).
LSB Justified standard (Right Justified).
PCM standard (with short and long frame synchronization on 16-bit channel frame or 16-bit data frame extended to 32-bit channel frame)
Master clock may be output to drive an external audio component. Ratio is fixed at 256 F ( h F i th di li f )256xFs (where Fs is the audio sampling frequency).
Support for DMA (16-bit wide).
STM32 Seminar November 2010230
I2S audio protocol (1/2)The I2S protocol is used for audio data communication between a microcontroller/DSP and an audio Codec/DAC.
The Data are coded according to a specific audio protocol (I2S Phillips/MSB/LSB/PCM) and are time-multiplexed on two channelsPhillips/MSB/LSB/PCM) and are time multiplexed on two channels (Left and Right).
The protocol uses three/four communication lines:CK : Serial clock SD : Serial data
I2SCK
MCLK
WS : Word Select, control signalMCLK : Master Clock signal (optional)
CK
SD
WS
Application Note is available from www.st.com/mcuAN2739: Using high-density STM32F103xx to play audio files with an external I²S audio
codec
STM32 Seminar November 2010
Data format and packet frameData frame format :
Programmable data size :16-, 24- or 32-bit data format selection
Programmable packet frame : 16-bit (for 16-bits data size) and 32-bits (for 16-, 24- and 32-bit data size).
1616--bit Right bit Right 1616--bit Left Databit Left Data
1616--bit data length bit data length 1616--bit packetbit packet
0xD70xD7
WSWS
DataData
1616--bit Left Databit Left DataI2S
CK (SCK)SD (MISO)
3232--bit packetbit packet0xD70xD7
WSWS
WS (NSS)
3232--bit packetbit packet
0xD730xD732424--bit databit datalength length
WSWS
MCLK *
2424--bit Left Databit Left Data
3232--bit packet bit packet 0xD7390xD739
WSWS* Optional feature activated by software
3232--bit Left Databit Left Data
3232--bit databit datalength length
STM32 Seminar November 2010232
Simplex Communication
I2S t l i l i ti d Th t d lI2S supports only simplex communication mode :
Simplex, three-wire synchronous audio transfer
The master and slave
configuration is managed
only by software. The I2C t l *
CK
STM32F10xCK
y y
master device is the CK
and WS generator.
I2C controls *
Audio Codec
ceeSD
WS
SD
WS The master/slave modes MCLKMCLK** A
nalo
g In
terf
ac
Dig
ital I
nter
face
Simplex synchronous audio transmissionSimplex synchronous audio transmission
and transmit/receive
directions can be switched
dynamically by software.y y y
** Optional feature activated by software
* Depends on the Codec control method
STM32 Seminar November 2010233
ST STANDARD PERIPHERAL LIBRARYLIBRARY
STM32 Seminar November 2010
Software libraries – speed time to market • ST software libraries free at www.st.com/mcu
C source code for easy implementation of all STM32 peripherals in any application– Standard library – source code for implementation of all standard
peripherals; code implemented in demos for STM32 evaluation board
– Motor control library – sensorless vector control for 3-phase brushless motors
• DSP library• DSP library – PID, IIR, FFT, FIR (free with license agreement)
• Free USB device library from ST: ANSI-C source code available, supporting many USB classes (mass storage, HID, DFU, CDC, audio)
STM32 Seminar November 201023
STM32 FW library – API structure
Application codelaye
r User Interrupt handlers
To be modified in project
stm32f10x_it.c
t 32f10 it hplic
atio
n
User library configuration
stm32f10x_it.h
stm32f10x_conf.h
App
g
stm32f10x ppp h
stm32f10x_ppp.c
laye
r Include this file to your application files
stm32f10x.hstm32f10x_ppp.h
AP
IW
HW Peripherals registers(PPP)
M32
HW
Do not modify– you can
share between
STM32 Seminar November 201023
ST share between
projects
STM32 – library – how to use it ?Function and constant for each peripheral has prefix with its name, like: GPIO, TIM1:
ie. GPIO_Init(), ADC_Channel_0, USART_IT_TXEMost of the settings is in 1fromN convention and allow to use concatenation, like:
GPIO_Pin_0 | GPIO_Pin_1, what means that pins 0 and 1 from will be configured in the same timeThere are predefined types in stm32f10x_type.h file, like:
u8 – unsigned charu16 unsigned shortu16 – unsigned shortRESET / SETFALSE / TRUEDISABLE / ENABLE
Most of the peripherals (PPP) has set of instruction:PPP_DeInit(...) – set all PPP register to its reset statePPP_Init(...) – validation of the configuration for the peripheralPPP_Cmd(ENABLE/DISABLE) – turn on/off PPP peripheral (not affects its clock)PPP_ITConfig(...) – configuration (on/off) of sources of interrupts for PPP peripheralPPP_GetFlagStatus(...) – read flags from the peripheral (polling)PPP ClearFlag( ) clear flags from the peripheralPPP_ClearFlag(...) – clear flags from the peripheralPPP_ClearITPendingBit(...) – clear IRQ flag
STM32 Seminar November 2010
STM32 VALUE-LINE DISCOVERY KITDISCOVERY KIT
STM32 Seminar November 2010
STM32 Discovery-kit
Development Toolchain supportECLIPSE Dev Tools : Free Atollic TrueSTUDIO®ECLIPSE Dev Tools : Free Atollic TrueSTUDIO® lite version with unlimited code-size and usage-time.IAR EWARMKEIL MDK-ARMKEIL MDK-ARM
Price: $9.90 Large number of software examples available atwww.st.com/stm32-discovery for a quick start to evaluate and develop with the STM32 Value line
STM32 Seminar November 201024
p
STM32 Value line Discovery Board
On-board ST-LINK with selection mode switch to use the kit as stand-alone ST-LINK with SWD connector
Designed to be powered by USB or by t l 5V 3 3V l
ST-LINK
external power 5V or 3.3V supply
Can supply target application with 5 Volts or 3 Volts
SWD connector
Volts or 3 Volts
Two User LEDs (Green and Blue)
84mm
STM32F100RBT6B
User button
One user Push Button
E i h d f ll QFP64 I/O
User button
Led GreenLed Blue
Extension header for all QFP64 I/Os for quick connection to prototyping board or easy probing 42mm
STM32 Seminar November 20102
STM32 Discovery Web-Supportwww.st.com/stm32-discoveryManuals, Getting started, examples...For Keil, IAR and Atollic
Forum with dozens of posts
STM32 Seminar November 201024
Thank You !
STM32 Seminar November 2010247