2. Binary Decision Diagrams Fachgebiet Rechnersysteme 1 2 ...

2. Binary Decision Diagrams 1

2 Binary Decision DiagramsFachgebiet Rechnersysteme

2. Binary Decision DiagramsVerification Technology

Content

2.1 BDD concepts2 2 Variable orderings2.2 Variable orderings2.3 OBDD algorithms2 4 FDD´s and OKFDD´s2.4 FDD s and OKFDD s2.5 Integer valued decision diagrams

The problem of logic verification: show that two circuits implement the same boolean functionp

2.1 BDD concepts

Problem: efficient representation of Boolean functions

2.1 BDD concepts

Problem: efficient representation of Boolean functions DNF: linear for OR of n variables, exponential for

XORXOR Reed-Muller: linear for XOR of n variables,

exponential for OR Problem: efficient application of Boolean operations

example: pDNF Negation DNF, e.g.:

ab + cd + ef + gh (ab + cd + ef + gh) ?ab + cd + ef + gh (ab + cd + ef + gh) ? Possible solution in many cases: binary decision

diagrams (BDD´s)d ag a s ( s)

2. Binary Decision Diagrams 42.1 BDD concepts

Investigated systematically first by R. Bryant (CMU) Seminal paper by Bryant in ´86 Seminal paper by Bryant in 86

Early work by Shannon ~ 1940 (relais-networks) Revolutionary impact on logic synthesis logic Revolutionary impact on logic synthesis, logic

verification, etc. Many modern CAD-tools employ BDD´s Many modern CAD tools employ BDD s

0 0 0 0 0a b c d f

Idea: decompose a function into two sub-0 0 0 0 0

0 0 0 1 00 0 1 0 00 0 1 1 0

functions which do not depend on a certain variable e g x0 0 1 1 0

0 1 0 0 00 1 0 1 0

variable, e.g., x1

0 1 1 0 00 1 1 1 01 0 0 0 01 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 01 0 1 1 01 1 0 0 01 1 0 1 01 1 0 1 01 1 1 0 01 1 1 1 1

0 0 0 0 0a b c d f

Idea: Decompose a function into two sub-0 0 0 0 0

0 0 0 1 00 0 1 0 00 0 1 1 0

functions which do not depend on a certain variable e g x0 0 1 1 0

0 1 0 0 00 1 0 1 0

f(0, b, c, d) variable, e.g., x1

Apply Boole´s expansion theorem in a systematic

0 1 1 0 00 1 1 1 01 0 0 0 0

theorem in a systematic way to all variables

Represent result 1 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 0

graphically

1 0 1 1 01 1 0 0 01 1 0 1 0

f(1, b, c, d)

1 1 1 0 01 1 1 1 1

f *f( ) *f( )2.1 BDD concepts

0 0 0 0 0a b c d f

ff = a*f(0, b, c, d) + a*f(1, b, c, d)

0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 0 a0 0 1 1 00 1 0 0 00 1 0 1 0

f(0, b, c, d) a0 1

0 1 1 0 00 1 1 1 01 0 0 0 0

0 0 0 0 0 0 0 0f(0, b, c, d) f(1, b, c, d)

1 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 0

0 0 0 00 0 1 00 1 0 0

1 0 1 1 01 1 0 0 01 1 0 1 0

f(1, b, c, d) 0 1 1 01 0 0 01 0 1 0

0 1 1 01 0 0 01 0 1 0

1 1 1 0 01 1 1 1 1

1 0 1 01 1 0 01 1 1 0

1 0 1 01 1 0 01 1 1 1

The application of Boole´s expansion theorem to all variables leads to a decision tree. Example: XOR in 3 variables

a b c a b c a b c

a0 10 0 0 0

0 0 1 1

0 1 0 10 1 1 01 0 0 1

1 0 0 11 0 1 01 1 0 0

0 1 0 10 10 11 1 1 1

1 10 1 1 0 0 0Function values

The application of Boole´s expansion theorem to all variables leads to a decision tree.

a b c a b c a b c Example: XOR in 3 variables

a0 10 0 0 0

0 0 1 1

0 1 0 10 1 1 01 0 0 1

1 0 0 11 0 1 01 1 0 01 1 1 1 0 1 0 10 10 11 1 1 1

1 10 1 1 0 0 0Function values

Variable ordering: order in which Boole's expansion theorem is appliedpp

order a b c a0 1

order a, b, c

c0 1 0 1 0 10 10 1

1 10 1 1 0 0 0

Concepts: NodesEd l b lliEdge labellings

bb Directed edgesb

(Direct) successors of node a

Concepts:Root node

a0 1 Paths

c0 1 0 10 10 1

1 10 1 1 0 0 0

Leafs or Terminal nodes

Decision trees are ordered (identical variable ordering on all paths) or freeg p )

— Example of a free decision tree:a

b c0 1b

1 10 1 1 0 0 0

A fully expanded decision tree has 2n leaf nodes Example of a (free) decision tree which is not fully Example of a (free) decision tree which is not fully

expanded:a

b c0 1b

11 0 0

Observation: there are identical sub-trees

b b0 1b

1 10 1 1 0 0 0

Observation: there are identical sub-trees

b b0 1b0 1

0 1 1 0

Merging identical sub-trees results in a decision-graph

0 1a b c a b c

0 01 10 0 0 0

0 0 1 10 1 0 1

c c1 1

0 1 0 10 1 1 01 0 0 11 0 1 0 0 0

1 11 0 1 01 1 0 01 1 1 1

a b c a b c

0 01 10 0 0 0

0 0 1 10 1 0 1

c c1 1

0 1 0 10 1 1 01 0 0 11 0 1 0 0 0

1 11 0 1 01 1 0 01 1 1 1

0 1"0-part" "1-part"

Shannon: A symbolic analysis of relay and switching circuits (1938)circuits (1938) Size of the networks grows linearly in the number of

variables

Some simple examples of BDD's:

010 1 01

0 b0 1

0 1 0 1

AND-, OR-, XOR-operation in n variablesx x

0x1 x1

x2x2 x2

0 01 1

..xn xn

0 01 1

0 1 0 1

#nodes grows linearly in #variables

2.1 BDD concepts

— Example:SN 74181 ALU:

— SN 74181 BDD ("shared BDD"):2.1 BDD concepts

g c4 p f3 f2 aeqb f1 f0

s3s2s1s0b3a3b2a3

a2b1a2

a1b0a0mmc

One path to the 1 leaf-node corresponds to a product –an implicant of the function. Example:p p

a0 1a b c a b c

b b1 10 0 0 00 0 1 1

0 00 1 0 10 1 1 01 0 0 1 c c

0 01 1

1 0 0 11 0 1 01 1 0 0

01 1 1 1

2 Problems: Given a binary decision diagram Given a binary decision diagram.

How to derive the Boolean function represented by the BDD?

Given a Boolean function. How to derive the BDD for it?

First: BDD Boolean function

A node v of a BDD is characterized by a triple (x, v0 ,v1), where v0 ,v1 are the successors of v0 , 1

The leaf nodes 0 and 1 represent the Boolean functions 0 and 1

According to Boole's expansion theorem, the Boolean function bf(v) is associated with node v as follows (where var(v) is the variable of node v):var(v) is the variable of node v):

bf(v) = var(v)· bf(v0) + var(v)· bf(v1)f f 0 f 1

— Example: which Boolean function is represented by the following BDD?y g

The function associated with a node can be

determined only if the functions associated with the successor nodes are known

bf(v) = var(v)· bf(v0) + var(v)· bf(v1)

"Bottom-up procedure": 1. Step

Functions 0 and 1Functions 0 and 1

"Bottom-up procedure": 2. Step

0 b bf(v) = var(v)· bf(v0) + var(v)· bf(v1)

1 = b · 0 + b · 1 = b

"Bottom-up procedure": 3. Stepbf( ) ( ) bf( ) ( ) bf( )

bf(v) = var(v)· bf(v0) + var(v)· bf(v1)

= a · 0 + a · b = a · b1

0 b bf(v) = var(v)· bf(v0) + var(v)· bf(v1)

1 = b · 0 + b · 1 = b

There are many variants of binary decision diagrams Most useful and common: OBDD's (Ordered Binary Most useful and common: OBDD s (Ordered Binary

Decision Diagrams, Bryant 1986) OBDD properties:OBDD properties:

Ordered : The variables appear in a fixed ordering on all paths

— Technically, an index (a positive integer) is associated with each variable index(var(v))

— For each node v with successors v0 and v1 we have: index(var(v)) < index(var(v0)) undindex(var(v)) < index(var(v ))index(var(v)) < index(var(v1))

a b c i bl

a b c variableorder a, b, c index(a) = 1

index(b) = 2 b0 1b

0 1index(b) = 2

index(c) = 3c

index(c) 3

1 10 1 1 0 0 0

OBDD properties (cont'd.): Reduced: Reduced:

— The function represented by one node is different from the functions of all other nodes

— The two successors of each node are distinct

— Reduction example:

a0 1 a10

b0 1 0

1 1 1 0 01

Several representations of 1

Identical 0

1Identical successors

Simplified representations exist, e.g., 1-edges to the right 0-edges to the left 1-edges to the right, 0-edges to the left Edges to 0 omitted etc etc.

— Example: (a b) · (c d) · (e f) or: 0 edges are dashed lines

ab b or: 0 edges are dashed lines

all0 d de otherse

Now: Boolean function OBDD Example above: (a b) · (c d) · (e f) Example above: (a b) · (c d) · (e f) Let

F (a b) (c d) (e f) (a b) r

Variable ordering a, b, c, d, e, f Following Boole's expansion theorem, we have the

( ) ( ) ( ) ( )

Following Boole s expansion theorem, we have the following cofactors of F w.r.t. a

F (1 b) r b rF (0 b) r b r

F (1 b) r b ra F (0 b) r b ra

More expansions:aa

F (1 b) r b ra F (0 b) r b ra

b b00 1

F F rab ab F 0ab F 0ab etc.

The problem of reduction: In the example above it was easy to detect F F r In the example above it was easy to detect

and to merge the nodes for and Redundant nodes have to be removed

F F rab ab FabFab

Redundant nodes have to be removed Redundant nodes

— Either represent the same functionEither represent the same function— Or have identical successors (easy to detect)

How to know that two nodes represent the same function? How to know that two nodes represent the same function?

Two functions

aa faaff aa gaagg are equal iff they have identical cofactors

a 1 1 fa

a 1 1 ga

c f c g

fa fa ga ga

If we presume that all successor nodes of two nodes represent distinct functions then the two nodes represent p pidentical functions iff the direct successor nodes are pairwise identical

a0 1 0 10 1

f f g gfa faga ga

This results in a simple bottom-up-procedure: redundant nodes are eliminiated in theredundant nodes are eliminiated in the bottom-level first, the in the second level, etc.

c0 1 0 1 0 1

0 10 1

0 1 1 0 0 0 1. Step:1. Step:0/1 leafsa0 1

allothers

2. Step:d

a 12.1 BDD concepts

c nodesb

0 1b0 1

allothers

0 ccall

others

3. Stepb nodes

b nodes

allothers0 cc

We can decide that the two b nodes do notWe can decide that the two b-nodes do not represent the same function by means of the c-nodes

Example: derive the OBDD for the following function, variable order r e gvariable order r,e,g

r e g p p = eg + rg + reg

0 0 0 0 0 0 1 1 0 1 0 1

pr = eg + g = g 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0

23 = 8 cases pr = eg + eg 1 0 1 0 1 1 0 1 1 1 1 0

Traffic-rLight

Checkereg

pr = eg + g = g

+p = eg + rg + reg r

pr = eg + eg p g g g

0 10 1

Reduction was necessary in the original concept by R. Bryant (1986), but can be avoided completely (s. Sect. 2.3) y ( ), p y ( )

OBDD´s can be implemented easily by means of 2:1-Multiplexorsp

x0 1 x

fxfx_ & &

fx_ fxx

— Example:a

0 1a10

1 b0 1

c0 c00 1 c0

Given a certain variable ordering, OBDD´s are canonical representations of Boolean functions, i.e., there exists p , ,exactly one OBBD-representation for each Boolean function

Two circuits implementing the same function have identical OBDD's a 10

b b10 0

OBDD´Ci it 12.1 BDD concepts

OBDD´s&

Circuit 1:

Circuit 2: =1

Q=1 =1

2.2 Variable Orderings2.2 Variable Orderings

The variable ordering has a critical impact on the size of the OBDD (= #nodes)

There are static and d namic proced res to determine There are static and dynamic procedures to determine "good" orderings

2. Binary Decision Diagrams 522.2 Variable orderings

The number of nodes of a OBDD depends critically on the variable orderingg Classical example (Bryant 1986):

f = x1x2 + x3x4 + x5x6x1 x1 10

x3 0 10 11x3

10x5 x5x5 x5

0 1 0 1 0

x40 1x2 x2x2 x2

11x4 x4

0 011 00

0 1 x60 1

x4 x4 11 00

Example: n-bit adder:— Order R1: an, bn, an-1, bn-1,..., a0, b0

— Order R2: an, an-1,..., a0, bn, bn-1,..., b0

n= 8 16 32 64

time 0 02 0 03 0 11 0 19time 0.02 0.03 0.11 0.19#nodes 35 75 155 315R1:

time 0.39 16.34#nodes 750 196574R2:

Calculating the best order may result in exponential run time

For a given circuit, "good" orderings can be heuristically determined

— Example: Distribution of a "weight"1/4

x 1/21/41/2

1/21/41/2

Sum of weights: x=1/2, y=1/4, z=1/4, first use x for expansion

— Delete selected variable and distribute weight againweight again

1/21/43/4

1/21/2

Sum of weights : y=3/4, z=1/4, next use y for expansion

— Order: x, y, z

Sifting: dynamic ordering procedure (Rudell ICCAD´93) Basic step: exchange two adjacent variables (Fujita Basic step: exchange two adjacent variables (Fujita

et al. EDAC´91)

b b1 10 0

0 01 1

Principle: exchange 0-1 and 1-0 path

c c1 10 0

g0 g1 g2 g3

b b1 10 0

g0 g2 g1 g3

1 1b b

0 01 1

1 1c c

0 01 1

Sifting-procedure: Calculate variable with max #nodes (the "thickest" Calculate variable with max. #nodes (the thickest

part of the OBDD) Shift variable over OBDD by pairwise exchange of y p g

adjacent variables Shift variable to a position where #nodes is minimal

MinimumMinimum

Movie "Sifting" by Stefan Höreth:

im Detail:2.2 Variable orderings

V3 V41 0

V4 V4 V3 V3

V5 V5 V5 V5

2.3 OBDD Construction2.3 OBDD Construction

2. Binary Decision Diagrams 912.3 OBDD construction

Principle: build OBDD while traversing the circuit from inputs to outputsp p

a OBDD-Package

C-ProgramTraverser

Traverser

C-ProgramC-Program 1c

gC-Program &b

0 OBDD-Package

C-ProgramTraverser

0 10 1

b1 Traverser

0 10 1

C-Programc

C-Programm 1C-program 1C-Program 1b

0 1 0 1c

gC-Programm &

0 1 0 1

0 OBDD-Package

C-ProgramTraverser

0 10 1

b1 a Traverser

0 10 1

bC-Program

C-Program 1c&

gC-Programm &b

0 1 0 1c c

0 1C-Program &

0 1 0 1 0 1

Orthogonality of Boole's expansion

f+g = x*(fx + gx) + x*(fx + gx),

f*g = x*(fx * gx) + x*(fx * gx),

f = x*fx + x*fx

* *fx fx gx gx

AND-operation of two OBDD´s Assumption: nodes are represented as triples Assumption: nodes are represented as triples

(x,v0,v1)

var low high

f tiaccess-functions

function AND(bdd1, bdd2):IF bdd1 0 OR bdd2 0 THEN t 0IF bdd1=0 OR bdd2=0 THEN return 0;ELSEIF bdd1=1 THEN return bdd2;ELSEIF bdd2=1 THEN return bdd1;ELSE var1:=var(bdd1);var2:=var(bdd2);( ); ( );IF var1=var2 THEN x:=var1; v0:= AND(low(bdd1), low(bdd2)),

v1:= AND(high(bdd1),high(bdd2));( g ( ), g ( ));ELSEIF index(var1) < index(var2) THEN x:=var1;

v0:= AND(low(bdd1), bdd2), ( ( ), ),v1:= AND(high(bdd1), bdd2);

ELSEIF ...IF v0 = v1 THEN return v0 ELSE return (x v0 v1);IF v0 = v1 THEN return v0 ELSE return (x,v0,v1); ...

bdd1 bdd2var1=a var2=c => index(var1) < index(var2)

x:=var1 := ax:=var1 := a v0:= and(low(bdd1),bdd2), v1:= and(high(bdd1),bdd2)

0 143 4

bdd1 bdd2var1=b var2=c => index(var1) < index(var2)

53 4 5

bdd1 bdd2var1=b var2=c => index(var1) < index(var2)

x:=var1 := bx:=var1 := b v0:= and(low(bdd1),bdd2), v1:= and(high(bdd1),bdd2)

c0 10 1

bdd1 bdd2var2=c => index(var1) < index(var2)x:=var1 := b

var1=bx:=var1 := b v0:= and(low(bdd1),bdd2), v1:= and(high(bdd1),bdd2)

bdd1 bdd2

bdd1 bdd2var2=c => index(var1) < index(var2)x:=var1 := bvar2=cvar1=bx:=var1 := bv0:= and(low(bdd1),bdd2), v1:= and(high(bdd1),bdd2)

c0 10 1

bdd1 bdd2

var1=a var2=c => index(var1) < index(var2)x:=var1 := ax:=var1 := a v0:= and(low(bdd1),bdd2), v1:= and(high(bdd1),bdd2)

bdd1 bdd2

var2=c => index(var1) < index(var2)x:=var1 := a

var1=ax:=var1 := a v0:= and(low(bdd1),bdd2), v1:= and(high(bdd1),bdd2)

bdd1 bdd2

var2=c => index(var1) < index(var2)x:=var1 := a

var1=ax:=var1 := av0:= and(low(bdd1),bdd2), v1:= and(high(bdd1),bdd2)

"OBDD-Packages" manage two tables: The unique table (ut) with entries: The unique table (ut) with entries:

x v0 v1

For uniqueness of OBDD'sFor uniqueness of OBDD s

The computed table (ct) with entries

Operation bdd1 bdd2 Result bdd

Stores previously calculated resultsStores previously calculated results

Reduction was needed in the original OBDD procedures OBDD uniquess is guaranteed by OBDD uniquess is guaranteed by

Checking in the unique-table (ut) if the OBDD was calculated beforecalculated before

Testing for identical successor nodes

In addition, it is checked in the computed table (ct) if the result was calculated before

Many steps of recursion may be saved

function AND(bdd1, bdd2):IF (AND,bdd1,bdd2,x) ct THEN return x;( )IF bdd1=0 OR bdd2=0 THEN return 0;ELSEIF bdd1=1 THEN return bdd2;ELSEIF bdd1=1 THEN return bdd2;ELSEIF bdd2=1 THEN return bdd1;ELSE var1:=var(bdd1);var2:=var(bdd2);IF var1=var2 THEN x:=var1; v0:= AND(low(bdd1), low(bdd2)),

v1:= AND(high(bdd1),high(bdd2));ELSEIF index(var1) < index(var2) THEN x:=var1;

v0:= AND(low(bdd1), bdd2), v1:= AND(high(bdd1), bdd2);

ELSEIFELSEIF ...IF v0 = v1 THEN return v0 ELSEIF (x,v0,v1) ut THEN put in ut; ELSE return (x,v0,v1); ...

The computed table is essential for the efficiency of the algorithms:g In principle, two additional steps of recursion may

result at each step the number of steps may grow exponentially

in the number of variables Using the computed table with entries

th b f i i d d t | 1|*| 2| h

the number of recursions is reduced to |n1|*|n2| where |n1| and |n2| are the number of nodes of bdd1 and bdd2, respectively, p y

*2.3 OBDD construction

11 0011 00

11 0011 00a b c d e f g

11 0011 00

a b c d e f g 11 00

11 00g

11 0011 00

*2.3 OBDD construction

11 00 11 00

11 00 11 00- * exponential inthe number of variables?

11 00 11 00- O(n1*n2) using thecomputed table !

11 00 11 00

11 00* &

General result: If two OBDD´s with m and n nodes are logically If two OBDD s with m and n nodes are logically

combined then the resulting OBDD has m*n nodes

This is due to the fact that not more than m*n distinct functions are generated!

Negated edges: The OBDD of a function f and the OBDD of the The OBDD of a function f and the OBDD of the

negated function are very similar: exchange the terminal nodes 0 and 1!

Orthogonality of negation: negate a function by negating it's cofactors

=Meansti

=negation

Problem: non-canonical representation!

Solution: — Only the 0-edge can be a negated edge — 1 terminal leaf only (or the dual version ...)

0 1 0 1 0 1 0 1

Examples: variable and negated variable

11 00 1 0 0 11 0

10 11 111

Example:XOR function

10 0 1

XOR function11 00

11 00 0 1

Cofactor calculation using OBDD's cof(x pol OBDD): x variable pol polarity 1 or 0 cof(x, pol, OBDD): x variable, pol polarity 1 or 0 Easy if variable = top-variable, e.g., cof(a, 0, OBDD):

0 1 0 1

Generally: Replace pointers to the variable by the pointer to the 1-(0-)successor:( )

f = cf = ac +abc f = ac

fb = cf ac +abc

fb = ac

0 1 0 1

— Example: determine the 0-cofactor for variable d:

11 00 11 00

1111 00

Functional substitution: substitute function g vor variable x The paper-and-pencil method is: replace all The paper-and-pencil method is: replace all

occurrences of x textually by g How to do that with a OBDD-representation?How to do that with a OBDD representation?

f[x g] = gfx + gfx

Rationale:

fx 0f = xfx + xfx

fx 0f = gfx + gfx

1fx 1fx

Functional substitution: substitute function g vor variable x

f[x g] = gfx + gfx

Note: x : (f(x g)) = [fx(0 g)] + [fx(1 g)] = fxg + fxg = f[x g] f[x g]

Functional substitution can be reduced to the application of the -operator

Using Boolean operations plus cofactor-calculation more advanced Boolean operations like the - and -quantifier and functional substitutions can be implementedimplemented

OBDD´s are used in many CAD-tools for synthesis, verification and simulation

Many public domain OBDD-packages Many are based on the ite(p, f, g)-operator (if p then f else g)Many are based on the ite(p, f, g) operator (if p then f else g) CUDD package (Boulder Univ.)

OBDD are very efficient decision procedures for propositional calculus and are integrated intopropositional calculus, and are integrated into many theorem provers like PVS and ACL2

2.4 FDD's and OKFDD's2.4 FDD s and OKFDD s

OBDD's are based on Boole's expansion theorem OBDD's represent the systematic decomposition in all

variablesvariables Q: Are there other types of "decomposition"? How many?

2. Binary Decision Diagrams 1262.4 FDD's and OKFDD's

Boole' expansion: fxfxf

There are more types of expansion (exactly two more):xx fxfxf

Positive Davio-expansion

)ff(xff

Negative Davio-expansion

)ff(xff xxx

Negative Davio expansion)ff(xff xxx

FDD´s (Functional Decision Diagrams, Kebschull et al. 92) f = f x*(f f ) f = fx x (fx fx)

— for x = 0 fx

for x = 1 f f f = f— for x = 1 fx fx fx = fx

Same graph structure, but different interpretation:

xBoolean differenceof f w.r.t. x

fx (fx fx)

FDD´s (Functional Decision Diagrams, Kebschull et al. 92) f = f x*(f f ) f = fx x (fx fx)

— for x = 0 fx

for x = 1 f f f = f— for x = 1 fx fx fx = fx

Same graph structure, but different interpretation:

fRule:

Rule: variable = 1 XOR both branchest t th l f f0 1 to get the value of f

fx (fx fx)

FDD´s are canonical representations FDD's obey a different rule of reduction: FDD s obey a different rule of reduction:

x0 10 1

0fx fx

(fx fx) : if the Boolean difference is 0then f does not depend on x

Orthogonality of XOR and AND for FDD´s: f g = f x*(f f ) g x*(g g ) = f g = fx x (fx fx) gx x (gx gx) =

(fx gx ) x*[(fx fx) (gx gx)] Yes!

f g = (fx x*(fx fx)) (gx x*(gx gx)) =(fx*gx) x*[fx * (gx gx) (fx fx ) *gx

(f f )*(g g )] No!(fx fx)*(gx gx)]

All 4 combinations have to be considered

All 4 combinations have to be considered for the AND of 2 FDD's

OBDD and FDD for 4-bit adder

OKFDD´s (Ordered Kronecker FDD´s, Drechsler et al. 94) Allows any of the three types of decomposition for Allows any of the three types of decomposition for

each variable The type of decomposition is stored in a

decomposition type list (DTL)f = a*[(0c*(01)) b*((0c*(01))1)] +

a*[0c*(01)]

a*[0c*(01)] = a*(cbc) + a*c

fffa0 1

p Davio

xx fxfxf

)ff(xff 0 b 1 p.Davio

1c0 p Davio

)ff(xff xxx

10 p.Davio )( xxx

OBDD's/FDD's/OKFDD'S in comparison OKFDD´s have OBDD´s and FDD´s as subclasses OKFDD s have OBDD s and FDD s as subclasses OBDD´s:

AND OR XOR of two OBDD´s of size n and m— AND, OR, XOR of two OBDD s of size n and m requires max. n*m operations

FDD´s/OKFDD´s: FDD s/OKFDD s:— XOR requires max. n*m, but AND and OR may

need exponentially many operations!y yHowever: #nodes of FDD/OKFDD may be

exponentially smaller than #nodes of the OBDD ( d i )OBDD (and vice versa)

Important for logic synthesis OKFDD´ d t i i th d iti t li t OKFDD´s: determining the decomposition-type list

(DTL) is an additional problem

The OBDD size grows only linearly in #variables for many circuits (AND, OR, XOR, adders, ALU's, etc.)y ( , , , , , )

Can all circuits be represented with linear (or polynomial) effort?

The theoretical answer is that there will never be any representation with this nice property for all circuits

While the OBDD's are very compact representations for many classes of circuits they fail for others ...

Example: multiplier circuits A0A1A2A30 0 0 0

P7 P6 P5 P4 P3 P2 P1 P0

Word length : 4 6 8

Interest in other types of decision diagrams

Word length : 4 6 8#OBDD nodes : 150 2.183 10.766

2.5 Integer-Valued Decision Diagrams

So far type Bn Bm now: type Bn Z:

2.5 Integer Valued Decision Diagrams

So far type Bn Bm, now: type Bn Z: MTBDD´s (Multi Terminal Binary Decision Diagrams,

Clarke et al. DAC ´93)Clarke et al. DAC 93) BMD´s (Binary Moment Diagrams, Bryant/Chen DAC ´ 95)

a 1 a rule:a0 1 a

0 1 rule: variable = 1 sum both branches

b b0 1 0 1

0 1 4 5 0 1 4

4a + bMTBDD

4a + bBMD

2. Binary Decision Diagrams 1372.5 Integer-valued decision diagrams

MTBDD:

f = (1 - x)*fx + x*fx

h * th dditi bt ti dwhere +, -, * are the addition, subtraction and multiplication, respectively

BMD: BMD:

f = fx + x*(fx - fx)

HDD´s (Clarke/Zhao): combination of MTBDD/BMD, one decomposition types for each variable ( OKFDD´s)decomposition types for each variable (~ OKFDD s)

Example of application (Fujita et a. ´96): Vector matrix operations employing MTBDD´s Vector-matrix operations employing MTBDD s Idea:

encode rows and columns by means of boolean— encode rows and columns by means of boolean variables

— elements ~ leafselements leafs Example 2*2 Matrix:

fxy fxy

y01 11 11

fxy fxy

y00 1 43 3

11 43 3

Type Bn Z and attributed edges EVBDD´s (Edge Valued Binary Decision Diagrams EVBDD s (Edge Valued Binary Decision Diagrams,

Lai et al. ICCAD ´93) *BMD´s (Multiplicative Binary Moment Diagrams,BMD s (Multiplicative Binary Moment Diagrams,

Bryant/ Chen DAC ´95)

a a rule:rule:a0 1

rule: variable = 1 =>add both branches,

lti l b i ht24

rule: add weight

b b0 1

multiply by weight0 1

0 1 40

4a + 2bEVBDD

4a + 2b*BMD

EVBDD:

f = a + (1 - x)*fx + x*fx

h + * th dditi bt ti dwhere +, -, * are the addition, subtraction and multiplication, respectively

*BMD: BMD:

f = m*(fx + x*(fx - fx))

K*BMD´s (Drechsler EDTC´96): one decomposition type for each variable (~ OKFDD´s HDD´s) additive +type for each variable (~ OKFDD s, HDD s), additive + multiplicative weights

*PHDD (Chen/Bryant ICCAD´97): multiplicative power PHDD (Chen/Bryant ICCAD 97): multiplicative power hybrid decision diagrams for floating-point circuits

For *BMD´s we have for an edge without weight:

f = fx + x*(fx - fx) = fx + x*fx.

*BMD´s are canonical representations provided that: 1. Rule:

0 fxfx

2. Rule: the weight on an edge equals the gcd of the weights of the successor edgesweights of the successor edges

x0 10 1

0 1w0/t w1/t

fx. fx

.fx fx

a leave "n" is a 1 node with weight n

— Example: *BMD for f = 4*x + 2f = f + x*(f - f )f = fx + x (fx - fx)= 2 + x*(6 - 2),

gcd(2, 4) = 2

x x0 1

1 10 1

2 4 1 2

— Next example: *BMD for f = 3*y + 4*x + 2f = fy + y*(fy - fy)y y ( y y)= (4*x + 2) + y*((4*x + 5) - (4*x + 2))= (4*x + 2) + y*3

3. Rule: sign of t is sign of left branch

x0 10 1

0 1w0/t w1/t

fx. fx

.fx fx

For *BMD´s with range {0, 1}, the boolean operations can be reduced to integer addition, subtraction and g ,multiplication:

f 1 ff 1 - ff and g f*gf or g f + g - f*gf xor g f + g - 2*f*g

Some example *BMD´s: 4 variable AND (a boolean function) 4 variable AND (a boolean function)

0 1OBDD 0 1*BMD

4 variable OR (a boolean function)

1x40 0 101

10OBDD *BMD

4 variable OR (a boolean function) x4= 0, x3 = 0, x2 = 1, x1 = 01

0x1 0 1

x3 x3-11

0 11x40

10OBDD *BMD

Example: 2-Bit multiplicationx *(y *21 +y *20)+x x y y

x0*(y1*21 +y0*20)+2*x1*(y1*21 +y0*20)

Result:

x1 , x0 y1 , y0

x *(y *21 +y *20)

(x1*21 +x0*20)*(y1*21 +y0*20) =20*x *(y *21 +y *20)+

0 1 x1*(y1*21 +y0*20)2 x0 (y1 2 +y0 2 )+21*x1*(y1*21 +y0*20)

0 12 y1*21 +y0*20

Classification schema of decision diagrams (based on Minato ´96): a

0 1 0 10 1

Shannon p Daviodecomposition mixed

FDDOBDD

Shannon p. Davio

ptype: mixed

OKFDDO O

BMDMTBDD Bn ZHDD

Bn Z,tt ib t d*BMDEVBDD attributed

edgesK*BMD

2.6 Bit-Vector Expressions

2.6 Bit Vector Expressions

Bit-vectors: Used for the compact representation of complex

digital hardwaredigital hardware More adequate than single bits in many cases

Examples: data paths arithmetic circuits— Examples: data-paths, arithmetic circuits, register-transfer-level (rtl) descriptions, storage elements, ...

Provided by many hardware description languages (HDL's) as a basic data-type

2. Binary Decision Diagrams 1532.6 Bit-vector expressions

— Example: specification of 74181 ALU Generic bit-vector function "A PLUS B"

S3 S2 S1 S0 M = H M = LCn = H M = L

Cn = L

L L L L F = not(A) F = A F = A PLUS 1L L L HL L H LL L H HL H L LL H L H

F = not(A+B)F = not(A) BF = 0F = not(A B)F (B)

F = A + BF = A + not(B)F = MINUS 1F = A PLUS A not(B)F (A B) PLUS A (B)

F = (A + B) PLUS 1F = (A + not(B)) PLUS 1F = 0F = A PLUS A not(B) PLUS 1F (A B) PLUS AB PLUS 1L H L H

L H H LL H H HH L L LH L L H

F = not(B)F = A BF = A not(B)F = not(A)+BF t(AB)

F = (A + B) PLUS A not(B)F = A MINUS B MINUS 1F = A not(B) MINUS 1F = A PLUS ABF = A PLUS B

F = (A + B) PLUS AB PLUS 1F = A MINUS BF = A not(B)F = A PLUS AB PLUS 1F = A PLUS B PLUS 1H L L H

H L H LH L H HH H L LH H L H

F = not(AB)F = BF = A BF = 1F = A + not(B)

F = A PLUS BF = (A + not(B)) PLUS ABF = A B MINUS 1F = A PLUS AF = (A + B) PLUS A

F = A PLUS B PLUS 1F = (A + not(B)) PLUS AB PLUS 1F = ABF = A PLUS A PLUSF = (A + B) PLUS A PLUS 1H H L H

H H H LH H H H

F = A + not(B)F = A + BF = A

F (A + B) PLUS AF = (A + not(B)) PLUS AF = A MINUS 1

F (A + B) PLUS A PLUS 1F = (A + not(B)) PLUS A PLUS 1F = A

Bit-vector functions are necessary for input/output specifications, i.e., for the abstraction from internal p , ,details

I/O-SpecificationSpecification

Q=1 =1

Typical bit-vector functions:Function Meaning Example:Function

FAE(A,N)ADC(A B C)

Meaning

fan-outdditi

Example:

FAE(1,3)="111"ADC(A,B,C)ADD(A,B)INC(A)

additionaddition moduloincrement

ADC("11","01",´1´)="101"ADD("11","01")="00"INC("111")="000"INC(A)

DCR(A)RSH(C,V)LSH(V C)

decrementrigth-shiftleft shift

INC( 111 ) 000DCR("111")="110"RSH(´0´,"111")="011"LSH("111" ´0´) "110"LSH(V,C)

ROL(A)ROR(A)

left-shiftrotate leftrotate right

LSH("111", 0 )="110"ROL("001")="010"ROR("010")="001"( )

MPX1(A,S)MINT(A,N)

multiplexor 1. Dim.minterm

( )MPX1("0010","10")=´1´MINT(A(1:2),0)=(not A(1)) and (not A(2))

GT(A,B)LESS(A,B)

A greater BA less B

(not A(1)) and (not A(2))GT("100","010")=1LESS("100","010")=0

Bit-vectors in VHDL Type bit vector predefined Type bit_vector predefined

signal X: bit_vector (1 to 16) or: (16 downto 1) Selection of single elements X(4) or slicesSelection of single elements X(4) or slices

X(2 to 4) Constant-denotation (B)"1001" Assignments X(2 to 4) <= X(8 to 10) Overloaded boolean primitives, e.g., g

"0101" AND "0011" = "0001" Concatenation &, e.g., X(2 to 4)&X(5 to 7) = X(2 to 7) ...

Verification problems: How to demonstrate the equality of arbitrary bit- How to demonstrate the equality of arbitrary bit-

vector expressions? Do we have to reason formally about tuples, etc.?Do we have to reason formally about tuples, etc.?

Decision procedure: procedure to decide the truth of a statement in some domain

For generic expressions (may contain expressions of arbitrary length), inductive reasoning is typically used Example: prove ADD(A, B) = ADD(B, A) for arbitrary

vectors A and B of the same length Typically a theorem prover is employed

— You have to derive the proof in large part by lfyourself

— The theorem prover checks if the proof is correctN t t t d d i t tiNot automated, needs user interaction

For fixed-length expressions, the problem becomes much simplerp Example: prove ADD(A, B) = ADD(B, A) for 32-bit

vectors A and B Several decision procedures exist:

The problem can be reduced to OBDD's The problem can be reduced to an integer-linear

programming (ILP) problem A specific decision procedure was given by Cyrluk et

al. (CAV´97) for a restricted repertoire of bit-vector functionsfunctions

Reduction to OBDD's ("bit-blasting"): Translate expression using bit-vector-functions into Translate expression using bit-vector-functions into

multi-level gate-networks— e.g., A PLUS B, where A and B are two 4-bite.g., A PLUS B, where A and B are two 4 bit

vectors, is transformed into the gate-network of a four-bit adder

Then as before !

vectorexpression 1

gatenetwork 1 OBDD 1

?vector

expression 2gate

network 2 OBDD 2

expression 2 network 2

Technique offers the general possibility to carry out proofs involving complex bit-vector expressionsp g p p Examples:

ADD(A, B) = ADD(B, A)

(ADD(A, B) > ADD(B, C)) (A>C)

(A>B) = NOT(ADD(0&A, 1&NOT(B))(1))

where A B C have fixed length by declarationwhere A, B, C have fixed length by declaration Typically takes < 1 sec. for 64-bit vectors

A > B = NOT (ADD(0&A, 1&NOT(B)))(1) BN

N´0´ ´1´

1 N+11

N 8 16 32 64 128CPU-timeN

1.8128

Example: verification of ALU´s Verification of VHDL-specification using bit- Verification of VHDL-specification using bit-

vector-operations vs. network of standard-cells

CPU-time

Wordlength

32-Bit ALU: 2 * 32 boolean functions in up to 77

CPU time 1.0 1.5 2.8 6.6

variables

Some references: Hassoun/Sasao (Eds ): Logic Synthesis and Hassoun/Sasao (Eds.): Logic Synthesis and

Verification, Springer— Book-Chapters on BDD's, SAT, EquivalenceBook Chapters on BDD s, SAT, Equivalence

checking Hachtel/Somenzi: Logic Synthesis and

Verification Algorithms, Springer

Written exam in the summer between 18 Juli and 7 October 2011 between 18. Juli and 7. October 2011 please follow Doodle link

http://www.doodle.com/y4igrfy6wcrmx24hhttp://www.doodle.com/y4igrfy6wcrmx24h

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