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Chapter 05Tutorial Using Verilog

Design a 4-bit up-down counter using behavioral level HDL

language

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Create a New Project

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Enter a Name and Location for the Project

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Create New File

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You can type Verilog on the New File

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Example (4 位元上下數計數器 )

in1

in2

s1

out

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Behavioral level

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Save

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Type “counter.v”

Module name and File name must the same.

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Add Source

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Select “counter.v”

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Select Verilog Design File

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Add New Source

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Select Test Bench Waveform

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Click OK

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Give Input Value

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Save

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Select “View Behavioral..” and Run

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See a HDL Test bench

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Select “Generate Expected..” and Run

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Result

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Result (cont.)

Question & Answer